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| 型号： | EPM9560RC240-15 |
| 文件页数： | 42/42页 |
| 文件大小： | 489K |
| 代理商： | EPM9560RC240-15 |
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Altera Corporation
9
MAX 9000 Programmable Logic Device Family Data Sheet
For registered functions, each macrocell register can be individually
programmed for D, T, JK, or SR operation with programmable clock
control. The flipflop can also be bypassed for combinatorial operation.
During design entry, the user specifies the desired register type; the
MAX+PLUS II software then selects the most efficient register operation
for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
By either global clock signal. This mode achieves the fastest clock-to-
output performance.
■
By a global clock signal and enabled by an active-high clock enable.
This mode provides an enable on each flipflop while still achieving
the fast clock-to-output performance of the global clock.
■
By an array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available. As shown in Figure 2, these global
clock signals can be the true or the complement of either of the global clock
pins (DIN1 and DIN2).
Each register also supports asynchronous preset and clear functions. As
shown in Figure 3, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear inputs to registers are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the dedicated global clear pin
(DIN3). The global clear can be programmed for active-high or active-low
operation.
All MAX 9000 macrocells offer a dual-output structure that provides
independent register and combinatorial logic output within the same
macrocell. This function is implemented by a process called register
packing. When register packing is used, the product-term select matrix
allocates one product term to the D input of the register, while the
remaining product terms can be used to implement unrelated
combinatorial logic. Both the registered and the combinatorial output of
the macrocell can feed either the FastTrack Interconnect or the LAB local
array.
相关PDF资料 |
PDF描述 |
|---|---|
| EPM9560RC240-20 | |
| EPM9560RC304-15 | |
| EPM9560RI208-15 | |
| EPM9560RI208-20 | |
| EPM9560RI240-15 | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM9560RC240-15YY | 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz CMOS Technology 5V 240-Pin RQFP 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz 5V 240-Pin RQFP |
| EPM9560RC240-20 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM9560RC304-15 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM9560RI208-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述: |
| EPM9560RI208-20 | 制造商:Altera Corporation 功能描述:IC MAX |
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