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参数资料
| 型号： | EPXA4 |
| 厂商： | Altera Corporation |
| 英文描述： | Excalibur Devices |
| 中文描述： | 神剑设备 |
| 文件页数： | 4/34页 |
| 文件大小： | 277K |
| 代理商： | EPXA4 |
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4
Altera Corporation
Excalibur EPXA4 Devices Errata Sheet
utilizes three extra logic elements in the device and adds minimal
corresponding delay to the bridge timing. If logic element usage or
bridge timing is critical to your design, you can disable the automatic
Quartus II routing option by adding the following parameter to the
defparam
section of the stripe instantiation file generated by the
MegaWizard
:
lpm_instance.xa_configuration_fix =
“
FALSE
“
If this routing option is disabled, you must use the hardware work
around described below to ensure correct functionality.
1
If you use this recommended software workaround, ensure
that the
Remove Redundant Logic Cells
option is not
selected for your project.
1
If the
Perform WYSIWYG Primitive Resynthesis
option is
selected for your project, you may receive warnings that the
stripe signals were not routed correctly. To eliminate the
warnings, re-run the MegaWizard in Quartus II version 2.2.
This creates an additional settings file (
alt_exc_stripe.esf
) to
ensure that the required logic elements are implemented.
■
Hardware work around
—ensure that the external clock that drives
MASTER_HCLK
is inactive before the PLD is put into reconfiguration
mode, and is enabled again only after the PLD enters user mode.
INIT_DONE
can be used only to activate the external clock. It should
not be used to disable the clock, for the following reason: when
reconfiguration begins,
INIT_DONE
does not drop to low in time to
prevent the error. You must use another method to disable the
external clock, such as using an external device to control the clock
input.
If a PLL in the PLD portion of the device is used to drive
MASTER_HCLK
, you must drive the PLL
CLKLK_ENA
signal with
INIT_DONE
so that the PLL output does not drive
MASTER_HCLK
before the device is in user mode. See
AN 115: Using the ClockLock &
ClockBoost PLL Features in APEX Devices
for information on enabling
the PLD PLLs with
INIT_DONE
.
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| EPZ3006G | Power Choke |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPXA4F1020C1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述:IC EXCALIBUR ARM 1020FBGA |
| EPXA4F1020C1ES | 制造商:Altera Corporation 功能描述:IC EXCALIBUR ARM 1020FBGA |
| EPXA4F1020C2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述:IC EXCALIBUR ARM 1020FBGA |
| EPXA4F1020C2ES | 制造商:Altera Corporation 功能描述:IC EXCALIBUR ARM 1020FBGA |
| EPXA4F1020C3 | 制造商:Altera Corporation 功能描述:IC EXCALIBUR ARM 1020FBGA |
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