参数资料
型号: ESDASC
英文描述: QUAD TRANSIL ARRAY FOR ESD PROTECTION
中文描述: 四TRANSIL ESD保护阵列
文件页数: 3/9页
文件大小: 79K
代理商: ESDASC
ESDAxxSC5 / ESDAxxSC6
3/9
The ESDA family has been designed to clamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage VCL.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL =VBR +RdIPP
Where Ipp is the peak current through the ESDA cell.
DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20
s and 10/1000s surges.
2.5 s duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20
s, the
2.5
s rectangular surge is well adapted. In
addition both rise and fall times are optimized to
avoid any parasitic phenomenon during the
measurement of Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
2s
tp = 2.5s
t
I
Ipp
Types
VBR
@IR
IRM @VRM
Rd
αTC
VF @IF
min.
max.
typ.
max.
typ.
max.
note 1
note 2
0V bias
VV
mA
AV
m
10
-4/°C
pF
V
mA
ESDA5V3SC5
ESDA5V3SC6
5.3
5.9
1
2
3
230
5
280
1.25
200
ESDA6V1SC5
ESDA6V1SC6
6.1
7.2
1
20
5.25
350
6
190
1.25
200
ESDA14V2SC5
ESDA14V2SC6
14.2
15.8
1
5
12
650
10
100
1.25
200
ESDA17SC6
ESDA19SC6
17
19
21
1
0.075
0.1
14
15
700
800
10
8.5
85
80
1.2
10
ESDA25SC6
25
30
1
24
1000
10
60
1.2
10
note 1 : Square pulse, Ipp = 15A, tp=2.5
s.
note 2 :
VBR = αT* (Tamb -25°C) * VBR (25°C)
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