参数资料
型号: ESDASC
英文描述: QUAD TRANSIL ARRAY FOR ESD PROTECTION
中文描述: 四TRANSIL ESD保护阵列
文件页数: 6/9页
文件大小: 79K
代理商: ESDASC
ESDAxxSC5 / ESDAxxSC6
6/9
TECHNICAL INFORMATION
The ESDA19SC6 is particularly optimized to perform ESD protection. ESD protection is achieved by
clamping the unwanted overvoltage. The clamping voltage is given by the following formula :
VV
R I
CL
BR
dpp
=+
As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
ESD PROTECTION
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended:
s
The ESDA19SC6 should be placed as close as possible to the input terminals or connectors.
s
The path length between the ESD suppressor and the protected line should be minimized.
s
All conductive loops, including power and ground loops should be minimized.
s
The ESD transient return path to ground should be kept as short as possible.
s
Ground planes should be used whenever possible.
ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT
To have a good approximation of the remaining voltages at both VI/O side, we provide the typical
dynamical resistance value Rd. By taking into account the following hypothesis :
Rg > Rd and Rload > Rd
we have:
VOutput
V
R
V
R
BR
d
g
=+
×
The results of the calculation done for Vg = 8 kV, Rg = 330
(IEC61000-4-2 standard), Vbr = 19 V (typ.)
and Rd = 0.80
(typ.) give:
VOuput = 38.4 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few nanoseconds at the output side.
ESD Surge
Voutput
Rload
Rg
Rd
VBR
Vg
Device
to be
protected
ESDA19SC6
Fig. A1: ESD clamping behavior (example)
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