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参数资料
| 型号： | EVAL-AD1940MINIBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD1940 MINI SIGMADSP |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频，音频处理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | AD1940 |
| 主要属性： | 单芯片多通道 28/56 位音频 DSP |
| 次要属性： | 均衡，交叉，低音增强，多频带动态处理，延迟等 |
| 已供物品： | 板，线缆，CD，电源，USB 适配器 |
| 产品目录页面： | 775 (CN2011-ZH PDF) |
| 相关产品： | AD1940YSTZ-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP AD1940YSTZRL-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP |
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AD1940/AD1941
Rev. B | Page 29 of
36
Table 38. Serial Output Control Register 1
(Channels 0–7) (2644)
Bits
Function
15
Dither enable
0 = Diabled
1 = Enabled
14
Internally link TDM streams into single,
16-channel stream
0 = Indepenent
1 = Linked
13
LRCLK polarity
0 = Frame begins on falling edge
1 = Frame begins on rising edge
12
BCLK polarity
0 = Data changes on falling edge
1 = Data changes on rising edge
11
Master/Slave
0 = Slave
1 = Master
10:9
BCLK frequency (master mode only)
00 = core_clock/24
01 = core_clock/12
10 = core_clock/6
11 = core_clock/3
8:7
Frame sync frequency (master mode only)
00 = core_clock/1536
01 = core_clock/768
10 = core_clock/384
6
Frame sync type
0 = LRCLK
1 = Pulse
5
Serial output/TDM mode control
0 = 8 Serial data outputs
1 = Enable TDM (8- or 16-channel) on
SDATA_OUT0
4:2
MSB position
000 = Delay by 1
001 = Delay by 0
010 = Delay by 8
011 = Delay by 12
100 = Delay by 16
101 Reserved
111 Reserved
1:0
Output word length, Channels 0–7
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = Reserved
Table 39. Serial Output Control Register 2
(Channels 8–15) (2645)
Bits
Function
15
Dither enable
0 = Disabled
1 = Enabled
14
Data capture serial out enable
(Uses SDATA_OUT7)
0 = Disable
1 = Enable
13
LRCLK polarity
0 = Frame begins on falling edge
1 = Frame begins on rising edge
12
BCLK polarity
0 = Data changes on falling edge
1 = Data changes on rising edge
11
Master/Slave
0 = Slave
1 = Master
10:9
BCLK frequency (master mode only)
00 = core_clock/24
01 = core_clock/12
10 = core_clock/6
11 = core_clock/3
8:7
Frame sync frequency (master mode only)
00 = core_clock/1536
01 = core_clock/768
10 = core_clock/384
6
Frame sync type
0 = LRCLK
1 = Pulse
5
Serial output/TDM mode control
0 = 8 serial data outputs
1 = Enable TDM on SDATA_OUT4 (8-channel)
or SDATA_OUT0 (16-channel)
4:2
MSB position
000 = Delay by 1
001 = Delay by 0
010 = Delay by 8
011 = Delay by 12
100 = Delay by 16
101 Reserved
111 Reserved
1:0
Output word length, Channels 8–15
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = Reserved
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