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参数资料
| 型号： | EVAL-AD1940MINIBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD1940 MINI SIGMADSP |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频，音频处理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | AD1940 |
| 主要属性： | 单芯片多通道 28/56 位音频 DSP |
| 次要属性： | 均衡，交叉，低音增强，多频带动态处理，延迟等 |
| 已供物品： | 板，线缆，CD，电源，USB 适配器 |
| 产品目录页面： | 775 (CN2011-ZH PDF) |
| 相关产品： | AD1940YSTZ-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP AD1940YSTZRL-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP |
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AD1940/AD1941
Rev. B | Page 13 of
36
I2C_FILT_ENB (AD1941)
I2C Spike Filter Enable/Disable. This enables (active low) the I2C
spike filter, which is used to prevent noise or glitches on the I2C
bus from improperly affecting the AD1941.
ADR_SEL
Address Select. This pin selects the address for the AD1940/
AD1941’s communication with the control port. This allows
two AD1940s to be used with a single CLATCH signal or two
AD1941s to be used on the same I2C bus.
RESETB
Active-Low Reset Signal. After RESETB goes high, the
AD1940/AD1941 goes through an initialization sequence where
the program and parameter RAMs are initialized with the
contents of the on-board boot ROMs. All registers are set to 0,
and the data RAMs are also set to 0. The initialization is com-
plete after 8,192 internal MCLK cycles (referenced to the rising
edge of RESETB), which corresponds to 1,366 external MCLK
cycles if the part is in 256 × fS mode. New values should not be
written to the control port until the initialization is complete.
VREF
Voltage Reference for Regulator. This pin is driven by an
internal 1.15 V reference voltage.
VDRIVE
Drive for External Transistor. The base of the voltage regulator’s
external PNP transistor is driven from this pin.
VSENSE
Digital Power Level. The voltage level on the VDD pins is
sensed on VSENSE. VSENSE should be tied to VDD.
VSUPPLY
Main Supply Voltage Level. This pin is tied to the board’s main
voltage supply. This is usually 3.3 V or 5 V.
VDD (4)
Digital VDD for Core. 2.5 V nominal.
GND (4)
Digital Ground.
PLL_VDD
Supply for AD1940/AD1941 PLL. 2.5 V nominal.
PLL_GND
PLL Ground.
ODVDD (3)
VDD for All Digital Outputs. The high levels of the digital
output signals are set on this pin. The voltage can range from
2.5 V to 5.0 V.
INVDD
Peak Input Voltage Level. The highest voltage level that the
input pin sees should be connected to INVDD. This is to
protect the chip inputs from voltage overstress. The voltage on
this pin must always be at or above the level of ODVDD.
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