参数资料
型号: EVAL-AD5372EBZ
厂商: Analog Devices Inc
文件页数: 24/29页
文件大小: 0K
描述: BOARD EVAL FOR AD5372
产品培训模块: DAC Architectures
标准包装: 1
DAC 的数量: 32
位数: 16
采样率(每秒): 540k
数据接口: 串行
设置时间: 20µs
DAC 型: 电压
工作温度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD5372
相关产品: AD5372BSTZ-REEL-ND - IC DAC 16BIT 32CH SER 64-LQFP
AD5372BSTZ-ND - IC DAC 16BIT 32CH SER 64-LQFP
AD5372/AD5373
Rev. C | Page 3 of 28
GENERAL DESCRIPTION
The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead
LQFP and LFCSP packages. The devices provide buffered
voltage outputs with a nominal span of 4× the reference voltage.
The gain and offset of each DAC can be independently trimmed
to remove errors. For even greater flexibility, the device is divided
into four groups of eight DACs. Two offset DACs allow the
output range of the groups to be altered. Group 0 can be adjusted
by Offset DAC 0, and Group 1 to Group 3 can be adjusted by
Offset DAC 1.
The AD5372/AD5373 offer guaranteed operation over a wide
supply range: VSS from 16.5 V to 4.5 V and VDD from 9 V to
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
The AD5372/AD5373 have a high speed serial interface that is
compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on reception of new data. All
the outputs can be updated simultaneously by taking the LDAC
input low. Each channel has a programmable gain and an offset
adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution (Bits)
Nominal Output Span
Output Channels
Linearity Error (LSB)
16
4 × VREF (20 V)
16
±4
14
4 × VREF (20 V)
16
±1
16
4 × VREF (20 V)
8
±4
14
4 × VREF (20 V)
8
±1
16
4 × VREF (12 V)
40
±4
14
4 × VREF (12 V)
40
±1
AD5372
16
4 × VREF (12 V)
32
±4
AD5373
14
4 × VREF (12 V)
32
±1
14
±8.75 V
32
±3
14
±8.75 V
40
±3
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