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参数资料
| 型号： | EVAL-AD5516-3EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION AD5516 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| DAC 的数量： | 16 |
| 位数： | 14 |
| 采样率（每秒）： | 750k |
| 数据接口： | 串行 |
| 设置时间： | 32µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5516-3 |
| 相关产品： | AD5516ABCZ-3-ND - IC DAC 12BIT 16CH BIPO 74-CSPBGA AD5516ABCZ-2-ND - IC DAC 12BIT VOUT 16CH 74-CSPBGA AD5516ABC-3-ND - IC DAC 12BIT 16CH 74-CSPBGA AD5516ABC-2-ND - IC DAC 12BIT 16CH 74-CSPBGA AD5516ABC-1-ND - IC DAC 12BIT 16CH 74-CSPBGA |
REV. B
–12–
AD5516
A data transfer is initiated by writing a word to the TX Register
after the SPORT has been enabled. In write sequences, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5516 on the falling edge of its SCLK. The
SPORT transmit control register should be set up as follows:
DTYPE
=
00, Right Justify Data
ICLK
=
1, Internal Serial Clock
TFSR
=
1, Frame Every Word
INTF
=
1, Internal Frame Sync
LTFS
=
1, Active Low Frame Sync Signal
LAFS
=
0, Early Frame Sync
SENDN =
0, Data Transmitted MSB First
SLEN
=
10011, 18-Bit Data-Words (SLEN = Serial Word)
Figure 6 shows the connection diagram.
AD5516*
ADSP-2106x*
SYNC
DIN
SCLK
TFS
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD5516 to ADSP-2106x Interface
AD5516 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5516, the MOSI output drives the serial data line
(DIN) of the AD5516. The SYNC signal is derived from a port
line (PC7). When data is being transmitted to the AD5516, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Data is transmitted
MSB first. In order to transmit 18 data bits, it is important to
left justify the data in the SPDR Register. PC7 must be pulled
low to start a transfer and taken high and low again before any
further read/write cycles can take place. A connection diagram is
shown in Figure 7.
AD5516*
MC68HC11*
SYNC
SCLK
DIN
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. AD5516 to MC68HC11 Interface
AD5516 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit (CKP) = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In this
example, I/O port RA1 is being used to provide a
SYNC signal
and enable the serial port of the AD5516. This microcontroller
transfers only eight bits of data during each serial transfer opera-
tion; therefore, three consecutive write operations are required.
Figure 8 shows the connection diagram.
AD5516*
PIC16C6x/7x*
SCLK
DIN
SYNC
SCK/RC3
SDI/RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. AD5516 to PIC16C6x/7x Interface
AD5516 to 8051
A serial interface between the AD5516 and the 80C51/80L51
microcontroller is shown in Figure 9. The AD5516 requires a
clock synchronized to the serial data. The 8051 serial interface
must therefore be operated in Mode 0. TxD of the microcon-
troller drives the SCLK of the AD5516, while RxD drives the
serial data line. P1.1 is a bit programmable pin on the serial port
that is used to drive
SYNC. The 80C51/80L51 provides the
LSB first, while the AD5516 expects MSB of the 18-bit word
first. Care should be taken to ensure the transmit routine takes
this into account.
AD5516*
8051*
SCLK
DIN
SYNC
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5516 to 8051 Interface
When data is to be transmitted to the DAC, P1.1 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the AD5516 clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As the DAC requires an 18-bit
word, P1.1 must be left low after the first eight bits are transferred
and brought high after the complete 18 bits have been transferred.
DOUT may be tied to RxD for data verification purposes when
the device is in Daisy-Chain Mode.
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