参数资料
型号: EVAL-AD5542ASDZ
厂商: Analog Devices Inc
文件页数: 24/24页
文件大小: 0K
描述: BOARD EVAL FOR AD5542
标准包装: 1
系列: nanoDAC™
DAC 的数量: 1
位数: 16
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
设置时间: 1µs
DAC 型: 电压
已供物品:
已用 IC / 零件: AD5542
AD5512A/AD5542A
Rev. A | Page 9 of 24
NC = NO CONNECT
1
2
3
4
5
6
7
8
VOUT
AGNDF
AGNDS
NC
REFF
REFS
RFB
CS
16
15
14
13
12
11
10
9
VLOGIC
INV
DGND
DIN
SCLK
CLR
LDAC
VDD
AD5542A
TOP VIEW
(Not to Scale)
09199-
035
Figure 6. AD5542A 16-Lead TSSOP Pin Configuration
Table 8. AD5542A Pin Function Descriptions
Pin No.
Mnemonic
Description
1
R
FB
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2
V
OUT
Analog Output Voltage from the DAC.
3
AGNDF
Ground Reference Point for Analog Circuitry (Force).
4
AGNDS
Ground Reference Point for Analog Circuitry (Sense).
5
REFS
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to V
DD.
6
REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to V
DD.
7
NC
No Connect.
8
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
9
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
10
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the DAC register is cleared to the model selectable midscale.
12
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
13
DGND
Digital Ground. Ground reference for digital circuitry.
14
INV
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting
input in bipolar mode.
15
V
LOGIC
Logic Power Supply.
16
V
DD
Analog Supply Voltage, 5 V ± 10%.
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