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参数资料
| 型号： | EVAL-AD5545SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5545 |
| 标准包装： | 1 |
| 系列： | * |
AD5545/AD5555
Data Sheet
Rev. G | Page 4 of 24
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AC CHARACTERISTICS
Output Voltage Setting Time
tS
To ±0.1% full scale, data = zero scale to
full scale to zero scale
0.5
μs
Reference Multiplying BW
BW
VREF = 100 mV rms, data = full scale, C1 = 5.6 pF
6.9
MHz
DAC Glitch Impulse
Q
VREF = 0 V, data = midscale minus 1 to midscale
–2
nV-s
Feedthrough Error
VOUT/VREF
Data = zero scale, VREF = 100 mV rms,
f = 1 kHz, same channel
–81
dB
Digital Feedthrough
Q
CS = logic high and fCLK = 1 MHz
7
nV-s
Total Harmonic Distortion
THD
VREF = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz
–104
dB
Analog Crosstalk
CTA
VREFB = 0 V, measure VOUTB with VREFA = 5 V p-p
sine wave, data = full scale, f = 1 kHz to 10 kHz
–95
dB
Output Spot Noise Voltage
eN
f = 1 kHz, BW = 1 Hz
12
nV/√Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier and the AD8065 for the THD specification.
4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
TIMING DIAGRAMS
02918- 0- 003
A1
SDI
CLK
CS
tCSS
tDS
tDH
tCH
tCL
tLDAC
tCSH
tLDS
tLDH
LDAC
A0
INPUT REG LD
D1
D0
D15
D14
D13
D12
D11
D10
Figure 2. AD5545 18-Bit Data Word Timing Diagram
02918- 0- 004
A1
SDI
CLK
CS
tCSS
tDS
tDH
tCH
tCL
tLDAC
tCSH
tLDS
tLDH
LDAC
A0
INPUT REG LD
D1
D0
D13
D12
D11
D10
D09
D08
Figure 3. AD5555 16-Bit Data Word Timing Diagram
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