- 您现在的位置：买卖IC网 > PDF目录17104 > EVAL-AD5781SDZ (Analog Devices Inc)BOARD EVAL FOR AD5781 PDF资料下载
参数资料
| 型号： | EVAL-AD5781SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5781 |
| 标准包装： | 1 |
| DAC 的数量： | 1 |
| 位数： | 18 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 设置时间： | 1µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5781 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
AD5781
Data Sheet
Rev. D | Page 20 of 28
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid. The input shift register is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register. Once the write cycle is complete, the output
can be updated by taking LDAC low while SYNC is high.
Readback
The contents of all the on-chip registers can be read back via
the SDO pin. Table 8 outlines how the registers are decoded.
After a register has been addressed for a read, the next 24 clock
cycles clock the data out on the SDO pin. The clocks must be
applied while SYNC is low. When SYNC is returned high, the
SDO pin is placed in tristate. For a read of a single register, the
NOP function can be used to clock out the data. Alternatively,
if more than one register is to be read, the data of the first
register to be addressed can be clocked out at the same time the
second register to be read is being addressed. The SDO pin
must be enabled to complete a readback operation. The SDO
pin is enabled by default.
HARDWARE CONTROL PINS
Load DAC Function (LDAC)
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
output. Depending on the status of both SYNC and LDAC, one
of two update modes is selected: synchronous DAC updating or
asynchronous DAC updating.
Synchronous DAC Update
In this mode, LDAC is held low while data is being clocked into
the input shift register. The DAC output is updated on the rising
edge of SYNC.
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5781 can be reset to its power-on state by two means:
either by asserting the RESET pin or by utilizing the software
RESET control function (see Table 14). If the RESET pin is not
used, it should be hardwired to IOVCC.
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 18-bit clear code value is
programmed to the clearcode register (see Table 13). It is
necessary to maintain CLR low for a minimum amount of time
to complete the operation (see Figure 2). When the CLR signal
is returned high, the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 14).
相关PDF资料 |
PDF描述 |
|---|---|
| RCM08DRTF-S13 | CONN EDGECARD 16POS .156 EXTEND |
| ADZS-BF548-MPSKIT | KIT STARTER MULTIMEDIA BF548 |
| SCRH3D16A-1R5 | INDUCTOR SMD 1.5UH 1.55A 100KHZ |
| HSM06DRKI-S13 | CONN EDGECARD 12POS .156 EXTEND |
| ADZS-BF549-EZLITE | KIT EZLITE ADZS-BF549 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-AD5790SDZ | 制造商:Analog Devices 功能描述:AD5790 DAC EVALUATION BOARD 制造商:Analog Devices 功能描述:AD5790, DAC, EVALUATION BOARD 制造商:Analog Devices 功能描述:AD5790, DAC, EVALUATION BOARD, Silicon Manufacturer:Analog Devices, Silicon Core 制造商:Analog Devices 功能描述:AD5790, DAC, EVALUATION BOARD, Silicon Manufacturer:Analog Devices, Silicon Core Number:(Not Applicable), Kit Application Type:(Not Available), Application Sub Type:DAC, Features:20-bit Voltage Output DAC, Integrated Precision , RoHS Compliant: Yes |
| EVAL-AD5791SDZ | 功能描述:BOARD EVAL FOR AD5791 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5821AEBZ | 功能描述:BOARD EVAL FOR AD5821 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5821EBZ | 功能描述:BOARD EVALUATION FOR AD5821 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5821EBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:120 mA, Current Sinking, 10-Bit, I2C DAC |
发布紧急采购，3分钟左右您将得到回复。