- 您现在的位置：买卖IC网 > PDF目录17050 > EVAL-AD7401AEDZ (Analog Devices Inc)BOARD EVAL FOR AD7401 PDF资料下载
参数资料
| 型号： | EVAL-AD7401AEDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7401 |
| 标准包装： | 1 |
| 系列： | iCoupler® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 20M |
| 数据接口： | 串行 |
| 输入范围： | ±320 mV |
| 在以下条件下的电源（标准）： | 105mW @ 20MSPS |
| 工作温度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7401A |
| 已供物品： | 板 |
AD7401A
Rev. C | Page 16 of 20
DIGITAL FILTER
The overall system resolution and throughput rate is determined
by the filter selected and the decimation rate used. The higher
the decimation rate, the greater the system accuracy, as illus-
trated in Figure 26. However, there is a tradeoff between accuracy
and throughput rate and, therefore, higher decimation rates
result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
for higher decimation rates to be used, resulting in higher SNR
performance.
80
70
60
50
40
30
20
10
0
90
10
100
1k
1
DECIMATION RATE
S
NR
(
d
B)
SINC3
SINC2
SINC1
07
33
2-
02
6
Figure 26. SNR vs. Decimation Rate for Different Filter Types
A sinc3 filter is recommended for use with the AD7401A. This
filter can be implemented on an FPGA or a DSP.
(
)
()
3
1
)
(
=
Z
z
H
DR
where DR is the decimation rate.
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if
preferred.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
mclk1;
/*used to clk filter*/
input
reset;
/*used to reset filter*/
input
mdata1;
/*ip data to be
filtered*/
output [15:0] DATA;
/*filtered op*/
integer location;
integer info_file;
reg [23:0]
ip_data1;
reg [23:0]
acc1;
reg [23:0]
acc2;
reg [23:0]
acc3;
reg [23:0]
acc3_d1;
reg [23:0]
acc3_d2;
reg [23:0]
diff1;
reg [23:0]
diff2;
reg [23:0]
diff3;
reg [23:0]
diff1_d;
reg [23:0]
diff2_d;
reg [15:0]
DATA;
reg [7:0]
word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
/* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
MCLKIN
IP_DATA1
ACC1+
ACC2+
ACC3+
+
Z
+
Z
+
Z
07
33
2-
02
7
Figure 27. Accumulator
相关PDF资料 |
PDF描述 |
|---|---|
| HI5860SOICEVAL1 | EVALUATION PLATFORM SOIC HI5860 |
| REC5-0505DRW/H2/A | CONV DC/DC 5W 4.5-9VIN +/-05VOUT |
| REC5-483.3DRW/H2/C | CONV DC/DC 5W 36-72VIN +/-3.3V |
| GCM22DCMH | CONN EDGECARD 44POS .156 WW |
| ISL5961EVAL1 | ISL5961 -SOICEVALUATION PLATF |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-AD7401EB | 制造商:AD 制造商全称:Analog Devices 功能描述:Isolated Sigma-Delta Modulator |
| EVAL-AD7401EDZ | 功能描述:BOARD EVALUATION FOR AD7401 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:iCoupler® 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD74111EBZ | 功能描述:BOARD EVAL FOR AD74111 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| EVAL-AD74122EB-U1 | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-AD7414/15EB | 制造商:AD 制造商全称:Analog Devices 功能描述:【0.5C Accurate, 10-Bit Digital Temperature Sensors in SOT-23 |
发布紧急采购，3分钟左右您将得到回复。