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| 型号： | EVAL-AD7401EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7401 |
| 标准包装： | 1 |
| 系列： | iCoupler® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 20M |
| 数据接口： | 串行 |
| 输入范围： | ±320 mV |
| 在以下条件下的电源（标准）： | 100mW @ 20MSPS |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7401 |
| 已供物品： | 板 |
AD7401
Rev. D | Page 15 of 20
DIGITAL FILTER
A Sinc3 filter is recommended for use with the AD7401. This
filter can be implemented on an FPGA or possibly a DSP. The
following Verilog code provides an example of a Sinc3 filter
implementation on a Xylinx Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge if preferred.
Figure 29 shows the effect of using different decimation rates
with various filter types.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
mclk1;
/*used to clk filter*/
input
reset;
/*used to reset filter*/
input
mdata1;
/*ip data to be
filtered*/
output [15:0] DATA;
/*filtered op*/
integer location;
integer info_file;
reg [23:0]
ip_data1;
reg [23:0]
acc1;
reg [23:0]
acc2;
reg [23:0]
acc3;
reg [23:0]
acc3_d1;
reg [23:0]
acc3_d2;
reg [23:0]
diff1;
reg [23:0]
diff2;
reg [23:0]
diff3;
reg [23:0]
diff1_d;
reg [23:0]
diff2_d;
reg [15:0]
DATA;
reg [7:0]
word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
/* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
MCLKIN
IP_DATA1
ACC1+
ACC2+
ACC3+
+
Z
+
Z
+
Z
05
85
1-
02
4
Figure 26. Accumulator
Z = one sample delay
MCLKIN = modulators conversion bit rate
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*DECIMATION STAGE (MCLKIN/ WORD_CLK)
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;
always @ (word_count)
word_clk <= word_count[7];
/*DIFFERENTIATOR (including decimation stage)
Perform the differentiation stage (FIR) at a
lower speed.
WORD_CLK
ACC3
DIFF1
DIFF3
+
–
+
–
DIFF2
Z–1
–
+
–
Z–1
0
585
1-
0
25
Figure 27. Differentiator
Z = one sample delay
WORD_CLK = output word rate
*/
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