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| 型号： | EVAL-AD7622CBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7622 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 2M |
| 数据接口： | 串行，并联 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 70mW @ 2MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7622 |
| 已供物品： | 板 |
| 相关产品： | AD7622BSTZ-ND - IC ADC 16BIT DIFFERENTIAL 48LQFP AD7622BCPZ-ND - IC ADC 16BIT DIFFERENTL 48-LFCSP AD7622BSTZRL-ND - IC ADC 16BIT DIFFERENTL 48-LQFP AD7622BCPZRL-ND - IC ADC 16BIT DIFFERENTL 48-LFCSP |
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AD7622
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7622 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
diagrams of these methods.
While the AD7622 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7622 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 40 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the conversion result can be read while both CS
and RD are low. Data is shifted out MSB first with 16 clock
pulses and is valid on the rising and falling edges of the clock.
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
In this reading mode, it is recommended to pause digital
activity just prior to initiating a conversion (SCLK should be
held high or low). Once the conversion has begun, the reading
can continue. In addition, in this mode, the use of a slower
clock speed can be used to read the data because the total
reading time is the acquisition time, t8 + half of the conversion
Previous Conversion section).
Finally, in this mode only, the AD7622 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple converters
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 39. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.
SCLK
SDOUT
RDC/SDIN
AD7622
#1
(DOWNSTREAM)
AD7622
#2
(UPSTREAM)
BUSY
OUT
BUSY
DATA
OUT
SCLK
RDC/SDIN SDOUT
SCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
06
02
3-
03
7
Figure 39. Two AD7622 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 41 shows the detailed timing diagrams of this method.
During a conversion, while CS and RD are both low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both the rising
and falling edge of the clock. The 16 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 60 MHz when normal mode is
used, or 80 MHz when warp mode is used) is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase.
If the maximum throughput is not used, thus allowing more
acquisition time, then the use of a slower clock speed can be
used to read the data.
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相关代理商/技术参数 |
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| EVAL-AD7622EDZ | 功能描述:BOARD EVAL FOR AD7622 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7623CB | 制造商:Analog Devices 功能描述:EVAL KIT FOR 16BIT, 1.33 MSPS PULSAR ADC - Trays |
| EVAL-AD7623CBZ | 功能描述:BOARD EVALUATION FOR AD7623 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:PulSAR® 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7623EDZ | 功能描述:BOARD EVAL FOR AD7623 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7625EDZ | 功能描述:数据转换 IC 开发工具 Eval Board 16-BIT 5MSPS ADC I.C RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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