参数资料
型号: EVAL-AD7678CBZ
厂商: Analog Devices Inc
文件页数: 14/28页
文件大小: 0K
描述: BOARD EVAL FOR AD7678
标准包装: 1
系列: PulSAR®
ADC 的数量: 1
位数: 18
采样率(每秒): 100k
数据接口: 串行,并联
输入范围: ±VREF
在以下条件下的电源(标准): 31mW @ 100kSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7678
已供物品:
AD7678
Rev. A | Page 21 of 28
MASTER SERIAL INTERFACE
Internal Clock
The AD7678 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7678 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 33 and Figure 34 show
the detailed timing diagrams of these two modes.
Usually, because the AD7678 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
12
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t14
t20
t15
t16
t22
t23
t29
t28
t18
t19
t21
t30
t25
t24
t26
t27
03084-0-039
Figure 33. Master Serial Data Timing for Reading (Read after Convert)
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