参数资料
型号: EVAL-AD7693CBZ
厂商: Analog Devices Inc
文件页数: 10/24页
文件大小: 0K
描述: BOARD EVALUATION FOR AD7693
标准包装: 1
系列: PulSAR®
ADC 的数量: 1
位数: 16
采样率(每秒): 500k
数据接口: 串行
输入范围: ±VREF
在以下条件下的电源(标准): 18mW @ 500kSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7693
已供物品:
相关产品: AD7693BRMZRL7-ND - IC ADC 16BIT 500KSPS 10-MSOP
AD7693BCPZRL7TR-ND - IC ADC 16BIT 500KSPS 10-LFCSP
AD7693BRMZ-ND - IC ADC 16BIT 500KSPS 10-MSOP
AD7693BCPZRL-ND - IC ADC 16BIT 500KSPS 10LFCSP
AD7693
Rev. A | Page 18 of 24
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7693 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If multiple AD7693s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO
CNV
SCK
SDO
SDI
VIO
AD7693
0
6
394
-03
5
DIGITAL HOST
Figure 36. CS Mode, 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D1
D0
tDIS
SCK
12
3
15
16
17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
0
63
94
-03
6
Figure 37. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
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