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| 型号： | EVAL-AD7723CBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7723 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 1.2M |
| 数据接口： | 串行，并联 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 475mW @ 1.2MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7723 |
| 已供物品： | 板，CD |
| 相关产品： | AD7723BSZ-REEL-ND - IC ADC 16BIT SIGMA-DELTA 44MQFP AD7723BSZ-ND - IC ADC 16BIT SIGMA-DELTA 44MQFP |
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AD7723
Rev. C | Page 13 of 32
Table 8. Serial Mode Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
DGND/DB2
Tie to DGND.
2
DGND/DB1
Tie to DGND.
3
DGND/DB0
Tie to DGND.
4
CFMT/RD
Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid on the rising or
falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on the falling edge of the serial clock,
SCO. If CFMT is logic high, SDO is valid on the rising edge of SCO.
5
DGND/DRDY
Tie to DGND.
30
DVDD/CS
Tie to DVDD.
31
DGND/DB15
Tie to DGND.
32
DGND/DB14
Tie to DGND.
33
SCR/DB13
Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is equal to the CLKIN
frequency. A logic high sets it equal to one-half the CLKIN frequency.
34
SLDR/DB12
Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate is selected. A logic
low selects the high data rate. The high data rate corresponds to data at the output of the fourth decimation filter
(decimate by 16). The low data rate corresponds to data at the output of the fifth decimation filter (decimate by 32).
35
SLP/DB11
Serial Mode Low-Pass/Band-Pass Filter Select Input. With SLP set logic high, the low-pass filter response is selected.
A logic low selects band-pass.
36
TSI/DB10
Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE enables
the SDO output buffer when it is a logic high and vice versa. TSI is used when two AD7723s are connected to the
same serial data bus. When this function is not needed, TSI and DOE should be tied low.
37
FSO/DB9
Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depending on the logic
level of the SFMT pin, the FSO signal is either a positive pulse approximately one SCO period wide or a frame pulse
that is active low for the duration of the 16-data bit transmission.
38
SDO/DB8
Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial Mode 1 data
transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles.
Serial Modes 2 and 3 data transmissions last 16 SCO cycles.
40
SCO/DB7
Serial Clock Output.
41
FSI/DB6
Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output data register to an
external source and to allow more than one AD7723, operated from a common master clock, to simultaneously
sample its analog input and update its output register.
42
SFMT/DB5
Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO signal for Serial Mode 1.
A logic low makes the FSO output a pulse one SCO cycle wide at the beginning of a serial data transmission. With
SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of the 16-bit transmission.
For Serial Modes 2 and 3, SFMT should be tied high.
43
DOE/DB4
Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO pin. The active state
of DOE is determined by the logic level on the TSI pin. When the DOE logic level equals the level on the TSI pin, the
serial data output, SDO, is active. Otherwise, SDO is high impedance. SDO can be three-state after a serial data
transmission by connecting DOE to FSO. In normal operations, TSI and DOE should be tied low.
44
DGND/DB3
Tie to DGND.
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