参数资料
型号: EVAL-AD7767-2EDZ
厂商: Analog Devices Inc
文件页数: 22/25页
文件大小: 0K
描述: BOARD EVALUATION FOR AD7767
标准包装: 1
ADC 的数量: 1
位数: 24
采样率(每秒): 32k
数据接口: 串行
输入范围: ±VREF
在以下条件下的电源(标准): 8.5mW @ 32kSPS
工作温度: -40°C ~ 105°C
已用 IC / 零件: AD7767-2
已供物品: 板,CD
其它名称: Q3407966
AD7767
Rev. C | Page 5 of
24
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = 40°C (TMIN) to +105°C (TMAX),
unless otherwise noted.1
Table 3.
Parameter
Limit at tMIN, tMAX
Unit
Description
DRDY OPERATION
t1
510
ns typ
MCLK rising edge to DRDY falling edge
100
ns min
MCLK high pulse width
900
ns max
MCLK low pulse width
t4
265
ns typ
MCLK rising edge to DRDY rising edge (AD7767)
128
ns typ
MCLK rising edge to DRDY rising edge (AD7767-1)
71
ns typ
MCLK rising edge to DRDY rising edge (AD7767-2)
t5
294
ns typ
DRDY pulse width (AD7767)
435
ns typ
DRDY pulse width (AD7767-1)
492
ns typ
DRDY pulse width (AD7767-2)
tDRDY t5
ns typ
DRDY low period, read data during this period
tDRDY3
n × 8 × tMCLK
ns typ
DRDY period
Read OPERATION
t6
0
ns min
DRDY falling edge to CS setup time
t7
6
ns max
CS falling edge to SDO tristate disabled
t8
60
ns max
Data access time after SCLK falling edge (VDRIVE = 1.7 V)
50
ns max
Data access time after SCLK falling edge (VDRIVE = 2.3 V)
25
ns max
Data access time after SCLK falling edge (VDRIVE = 2.7 V)
24
ns max
Data access time after SCLK falling edge (VDRIVE = 3.0 V)
t9
10
ns min
SCLK falling edge to data valid hold time (VDRIVE = 3.6 V)
t10
10
ns min
SCLK high pulse width
t11
10
ns min
SCLK low pulse width
tSCLK
1/t8
sec min
Minimum SCLK period
t12
6
ns max
Bus relinquish time after CS rising edge
t13
0
ns min
CS rising edge to DRDY rising edge
Read OPERATION WITH CS LOW
t14
0
ns min
DRDY falling edge to data valid setup time
t15
0
ns max
DRDY rising edge to data valid hold time
DAISY-CHAIN OPERATION
t16
1
ns min
SDI valid to SCLK falling edge setup time
t17
2
ns max
SCLK falling edge to SDI valid hold time
SYNC/PD OPERATION
t18
1
ns typ
SYNC/PD falling edge to MCLK rising edge
t19
20
ns typ
MCLK rising edge to DRDY rising edge going into SYNC/PD mode
t20
1
ns min
SYNC/PD rising edge to MCLK rising edge
t21
510
ns typ
MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode
tSETTLING3
(592 × n) + 2
tMCLK
Filter settling time after a reset or power-down
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.
2 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
MCLK frequency is 1.024 MHz.
3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.
相关PDF资料
PDF描述
VE-B34-EY CONVERTER MOD DC/DC 48V 50W
0210490278 CABLE JUMPER 1.25MM .030M 22POS
EVAL-AD7799EBZ BOARD EVALUATION FOR AD7799
RCM15DCBH-S189 CONN EDGECARD 30POS R/A .156 SLD
EVAL-AD7785EBZ BOARD EVALUATION FOR AD7785
相关代理商/技术参数
参数描述
EVAL-AD7767EDZ 功能描述:BOARD EVAL AD7767 128KSPS 108DB RoHS:是 类别:编程器,开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率(每秒):94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源(标准):- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板,软件
EVAL-AD7780EBZ 功能描述:BOARD EVAL FOR AD7780 RoHS:是 类别:编程器,开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率(每秒):94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源(标准):- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板,软件
EVAL-AD7781EBZ 功能描述:BOARD EVAL FOR AD7781 RoHS:是 类别:编程器,开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率(每秒):94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源(标准):- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板,软件
EVAL-AD7782EB 制造商:Analog Devices 功能描述:READ ONLY, PIN CONFIGURED 24BIT SEGMA-DELTA ADC - Bulk
EVAL-AD7783EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk