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参数资料
型号： EVAL-AD7922CBZ
厂商： Analog Devices Inc
文件页数： 31/32页
文件大小： 0K
描述： BOARD EVAL FOR AD7922
标准包装： 1
ADC 的数量： 1
位数： 12
采样率（每秒）： 1M
数据接口： 串行
输入范围： 0 ~ Vdd
在以下条件下的电源（标准）： 15.5mW @ 1MSPS，5 V
工作温度： -40°C ~ 85°C
已用 IC / 零件： AD7922
已供物品： 板，CD
相关产品： AD7922ARMZ-REEL7-ND - IC ADC DUAL 12BIT 2CH 8MSOP
AD7922AUJZ-REEL7TR-ND - IC ADC DUAL 12BIT 2CH TSOT-23-8
AD7922ARMZ-REEL-ND - IC ADC DUAL 12BIT 2CH 8MSOP
AD7922ARMZ-ND - IC ADC 12BIT 1MSPS DUAL 8-MSOP
AD7912/AD7922
Rev. 0 | Page 8 of 32
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1
As shown in Figure 7, when fSCLK = 18 MHz and the throughput
is 1 MSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 1 s
With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the
requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 126 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
Timing Example 2
The AD7922 can also operate with slower clock frequencies. As
shown in Figure 7, when fSCLK = 5 MHz and the throughput rate
is 315 kSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 3.17 s
With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the
requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum tQUIET between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
04351-0-006
ZERO
X
12
34
5
13
14
15
16
X
CHN
STY
X
CHN
MOD
DB11
DB10
DB2
DB1
DB0
Z
t2
t6
t4
t8
t9
t3
t7
t5
t10
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-STATE
DIN
B
Figure 6. AD7922 Serial Interface Timing Diagram
04351-0-007
12
3
45
13
14
15
16
tQUIET
tACQUISITION
1/THROUGHPUT
12.5(1/fSCLK)
tCONVERT
BC
SCLK
CS
t10
t2
Figure 7. Serial Interface Timing Example
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