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参数资料
| 型号： | EVAL-AD7944EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7944 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 2.5M |
| 数据接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 输入范围： | 0 ~ 5 V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7944 |
| 已供物品： | 板 |
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AD7944
Rev. A | Page 20 of 28
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7944 is connected
to an SPI-compatible digital host that has an interrupt input. It
is available only in normal conversion mode (TURBO low).
The connection diagram is shown in Figure 28, and the corre-
sponding timing is given in Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a con-
version, selects CS mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion, irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other SPI
devices, such as analog multiplexers, but CNV must be returned
low before the minimum conversion time elapses and then held
low for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7944 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the optional 15th SCK falling edge, SDO returns
to high impedance.
If multiple AD7944 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended that this
contention be kept as short as possible to limit extra power
dissipation.
AD7944
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
IRQ
VIO
47k
TURBO
04658-
011
Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDO
D13
D12
D1
D0
tDIS
SCK
1
2
3
13
14
15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
TURBO = 0
SDI = 1
tCNVH
tACQ
tQUIET
(I/O QUIET
TIME)
04658-
012
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
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