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参数资料
| 型号： | EVAL-AD7944EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7944 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 2.5M |
| 数据接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 输入范围： | 0 ~ 5 V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7944 |
| 已供物品： | 板 |
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AD7944
Rev. A | Page 17 of 28
DIGITAL INTERFACE
Although the AD7944 has a reduced number of pins, it offers
flexibility in its serial interface modes.
In CS mode, the AD7944 is compatible with SPI, MICROWIRE,
QSPI, and digital hosts. In CS mode, the AD7944 can use either
a 3-wire or a 4-wire interface. A 3-wire interface that uses the
CNV, SCK, and SDO signals minimizes wiring connections,
which is useful, for example, in isolated applications. A 4-wire
interface that uses the SDI, CNV, SCK, and SDO signals allows
CNV, which initiates conversions, to be independent of the
readback timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
In chain mode, the AD7944 provides a daisy-chain feature that
uses the SDI input for cascading multiple ADCs on a single data
line similar to a shift register. Chain mode is available only in
normal conversion mode (TURBO low).
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. CS mode is selected if SDI
is high, and chain mode is selected if SDI is low. The SDI hold
time is such that when SDI and CNV are connected together,
chain mode is always selected.
In normal mode operation, the AD7944 offers the option of
forcing a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled in CS mode if CNV or
SDI is low when the ADC conversion ends (see Figure 29 and
Figure 33). TURBO must be kept low for both digital interfaces.
Table 9 lists the availability of each serial interface mode, with
and without the busy indicator, for the two conversion modes.
Table 9. Serial Interface Modes (CS
Serial Interface Mode
and Chain Mode) for
Each Conversion Mode (Turbo and Normal)
Conversion Mode
Turbo Mode
Normal Mode
CS Mode, 3-Wire
Without Busy Indicator
Yes
With Busy Indicator
No
Yes
CS Mode, 4-Wire
Without Busy Indicator
Yes
With Busy Indicator
No
Yes
Chain Mode
Without Busy Indicator
No
Yes
With Busy Indicator
No
Yes
When CNV is low, readback can occur during conversion or
acquisition, or it can be split across acquisition and conversion,
as described in the following sections.
A discontinuous SCK is recommended because the part is selected
with CNV low, and SCK activity begins to clock out data.
Note that in the following sections, the timing diagrams indicate
digital activity (SCK, CNV, SDI, and SDO) during the conversion.
However, due to the possibility of performance degradation,
digital activity should occur only prior to the safe data reading
time, tDATA, because the AD7944 provides error correction
circuitry that can correct for an incorrect bit decision during
this time. From tDATA to tCONV, there is no error correction, and
conversion results may be corrupted.
Similarly, tQUIET, the time from the last falling edge of SCK to
the rising edge of CNV, must remain free of digital activity.
The user should configure the AD7944 and initiate the busy
indicator (if desired in normal mode) prior to tDATA.
It is also possible to corrupt the sample by having SCK near the
sampling instant. Therefore, it is recommended that the digital
pins be kept quiet for approximately 20 ns before and 10 ns after
the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
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