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| 型号： | EVAL-AD7949EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD7949 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 10.8mW @ 250kSPS，5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7949 |
| 已供物品： | 板 |
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AD7949
Data Sheet
Rev. D | Page 26 of 32
GENERAL TIMING WITH A BUSY INDICATOR
Figure 37 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). As detailed previously, the data access should occur up
to safe data reading/writing time, tDATA. If the full CFG word is
not written to prior to EOC, it is discarded and the current
configuration remains.
At the EOC, if CNV is low, the busy indicator is enabled. In
addition, to generate the busy indicator properly, the host must
assert a minimum of 15 SCK falling edges to return SDO to
high impedance because the last bit on SDO remains active.
Unlike the case detailed in the General Timing Without a Busy
Indicator section, if the conversion result is not read out fully
prior to EOC, the last bit clocked out remains. If this bit is low,
the busy signal indicator cannot be generated because the busy
generation requires either a high impedance or a remaining bit
high-to-low transition. Because most SPI hosts are usually
limited to 8-bit or 16-bit bursts, this should not be an issue.
Additional clocks are not a concern because SDO remains high
impedance after the 15th falling edge.
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2nd EOC; thus, two dummy conversions are
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n 1).
ACQUISITION
(n – 1) UNDEFINED
ACQUISITION
(n)
ACQUISITION
(n + 1)
ACQUISITION
(n + 2)
PHASE
POWER
UP
EOC
START OF CONVERSION
(SOC)
EOC
CONVERSION
(n)
CONVERSION
(n + 1)
CONVERSION
(n – 2) UNDEFINED
tCONV
tCYC
tDATA
CNV
DIN
RDC
RAC
RSC
SDO
NOTES
1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.
2. A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,
A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
DATA (n)
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DIN
SDO
DATA (n + 1)
DATA (n)
DATA (n + 1)
DIN
CFG (n)
CFG (n + 2)
CFG (n + 1)
CFG (n + 3)
SDO
SCK
1
SCK
1n
n + 1
15
1
n
n + 1
15
1
n
n + 1
15
SCK
1
XXX
NOTE 1
NOTE 2
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n + 3)
CONVERSION
(n – 1) UNDEFINED
07
35
1-
03
7
DATA (n – 1)
XXX
DATA (n – 2)
XXX
DATA (n – 3)
XXX
DATA (n – 2)
XXX
DATA (n – 1)
XXX
Figure 37. General Interface Timing for the AD7949 With a Busy Indicator
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