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参数资料
| 型号： | EVAL-AD7983SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7983 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 1.33M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 输入范围： | 0 ~ VREF |
| 在以下条件下的电源（标准）： | 10.5mW @ 1.33MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7983 |
| 已供物品： | 板 |
AD7983
Rev. A | Page 20 of 24
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the
data reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 32, and the
corresponding timing is given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers, but
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7983 then enters the acquisition phase
and goes into standby mode. The data bits are clocked out, MSB
first, by subsequent SCK falling edges. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or SDI going high, whichever is
earlier, the SDO returns to high impedance.
AD7983 SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CS1
CLK
VIO
47k
CNV
SCK
06
97
4-
01
8
Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCONV
tCYC
ACQUISITION
tSSDICNV
ACQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SDI
tHSDICNV
SCK
CNV
SDO
tEN
D15
D14
D1
D0
tHSDO
12
3
15
16
17
tDSDO
tDIS
06
97
4-
0
19
Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
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