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| 型号： | EVAL-AD7983SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7983 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 1.33M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 输入范围： | 0 ~ VREF |
| 在以下条件下的电源（标准）： | 10.5mW @ 1.33MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7983 |
| 已供物品： | 板 |
AD7983
Rev. A | Page 22 of 24
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7983s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7983s is shown
in Figure 36, and the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest
to the digital host (see the AD7983 ADC labeled C in Figure 36)
is driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7983 then enters the acquisition phase and goes
into standby mode. The data bits stored in the internal shift
register are clocked out, MSB first, by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in the
chain outputs its data MSB first, and 16 × N + 1 clocks are required
to readback the N ADCs. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate and, consequently, more AD7983s in
the chain, provided the digital host has an acceptable hold time.
AD7983
C
SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CLK
CNV
SCK
AD7983
B
SDO
SDI
CNV
SCK
AD7983
A
SDO
SDI
CNV
SCK
06
97
4-
02
2
Figure 36. Chain Mode with Busy Indicator Connection Diagram
tCONV
tCYC
tSSDISCK
tSCKH
tSCK
tHSDISCK
tACQ
tDSDOSDI
tDSDODSI
ACQUISITION
tSSCKCNV
ACQUISITION
tSCKL
CONVERSION
tHSCKCNV
SCK
CNV = SDIA
SDOA = SDIB
SDOB = SDIC
SDOC
tEN
DA15
DA14
DA13
DB15
DB14
DB13
DC15
DC14
DC13
DB1DB0DA15
DA14
DA1DA0
DC1DC0DB15
DB14
DA0
DA1
DB0
DB1DA14
DA15
DA1DA0
tHSDO
12
3
15
16
17
4
18
19
31
32
333435
47
48
49
tDSDO
tDSDOSDI
0697
4-
023
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
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