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| 型号： | EVAL-ADAU1381Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/84页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADAU1381 |
| 标准包装： | 1 |
| 主要目的： | 音频编解码器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADAU1381 |
| 已供物品： | 板 |
| 相关产品： | ADAU1381BCBZ-RL7DKR-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCBZ-RL7CT-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCBZ-RL-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCPZ-RL7-ND - IC AUDIO CODEC STEREO LN 32LFCSP ADAU1381BCPZ-RL-ND - IC AUDIO CODEC STEREO LN 32LFCSP ADAU1381BCBZ-RL7TR-ND - IC AUDIO CODEC STEREO LN 30WLCSP ADAU1381BCPZ-ND - IC AUDIO CODEC STEREO LN 32LFCSP |
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ADAU1381
Rev. B | Page 16 of 84
Table 10. Pin Function Descriptions
Pin No.
LFCSP
WLCSP
Mnemonic
Type1
Description
1
A6
CM
A_OUT
VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs and
DACs. The material of the capacitors is not critical. This pin can be used to bias external
analog circuits, as long as they are not drawing current from CM (for example, the
noninverting input of an op amp).
2
C5
PDN
A_IN
Power-Down. Connecting this pin to GND powers down the chip. Resides in AVDD1
domain.
3
B6
AGND1
PWR
Analog Ground.
4
C6
AVDD1
PWR
Analog Power Supply. Should be equivalent to AVDD2.
5
D6
DVDDOUT
PWR
Digital Core Supply Decoupling Point. The digital supply is generated from an on-
board regulator and does not require an external supply. DVDDOUT should be
decoupled to DGND with a 100 nF capacitor.
6
E6
DGND
PWR
Digital Ground.
7
D5
GPIO
D_IO
Dedicated General-Purpose Input/Output.
8
C4
SCL/CCLK
D_IN
I2C Clock/SPI Clock.
9
E5
SDA/COUT
D_IO
I2C Data/SPI Data Output.
10
C3
ADDR0/CDATA
D_IN
I2C Address 0/SPI Data Input.
11
D4
ADDR1/CLATCH
D_IN
I2C Address 1/SPI Latch Signal.
12
E4
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from
IOVDD, which sets the highest allowed input voltage for the digital input pins. The
current draw of this pin is variable because it is dependent on the loads of the digital
outputs. IOVDD should be decoupled to DGND with a 100 nF capacitor.
13
E3
DAC_SDATA/GPIO0
D_IO
DAC Serial Input Data/General-Purpose Input and Output.
14
D3
ADC_SDATA/GPIO1
D_IO
ADC Serial Output Data/General-Purpose Input and Output.
15
E2
BCLK/GPIO2
D_IO
Serial Data Port Bit Clock/General-Purpose Input and Output.
16
C2
LRCLK/GPIO3
D_IO
Serial Data Port Frame Clock/General-Purpose Input and Output.
17
E1
MCKI
D_IN
Master Clock Input.
18
D2
MCKO
D_OUT
Master Clock Output.
19
D1
AVDD2
PWR
Analog Power Supply. Should be equivalent to AVDD1.
20
C1
SPN
A_OUT
Speaker Amplifier Negative Signal Output.
21
N/A
NC
No Connect.
22
B1
SPP
A_OUT
Speaker Amplifier Positive Signal Output.
23
A1
AGND2
PWR
Speaker Amplifier Ground.
24
N/A
NC
No Connect.
25
B2
AOUTR
A_OUT
Line Output Amplifier, Right Channel.
26
A2
AOUTL
A_OUT
Line Output Amplifier, Left Channel.
27
B3
RMIC/RMICN/MICD2
A_IN
Right Channel Input from Single-Ended Source/Right Channel Input from Negative
Pseudo Differential Source/Digital Microphone Input 2.
28
A3
RMICP
A_IN
Right Channel Input from Positive Pseudo Differential Source.
29
B4
LMICP
A_IN
Left Channel Input from Positive Pseudo Differential Source.
30
A4
LMIC/LMICN/MICD1
A_IN
Left Channel Input from Single-Ended Source/Left Channel Input from Negative
Pseudo Differential Source/Digital Microphone Input 1.
31
B5
BEEP
A_IN
Beep Signal Input.
32
A5
MICBIAS
PWR
Microphone Bias.
THERM_PAD
(Exposed Pad)
Exposed Pad. The exposed pad is connected internally to the ADAU1381 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is
recommended that the pad be soldered to the ground plane.
1 A_OUT = analog output, A_IN = analog input, PWR = power, D_IO = digital input/output, D_OUT = digital output, and D_IN = digital input.
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