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| 型号： | EVAL-ADCMP553BRMZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADCMP553BRMZ |
| 标准包装： | 1 |
| 主要目的： | 接口，比较器 |
| 已用 IC / 零件： | ADCMP553 |
| 已供物品： | 板 |
| 相关产品： | ADCMP553BRMZ-ND - IC COMPARATOR PECL/LVPECL 8MSOP |
ADCMP551/ADCMP552/ADCMP553
Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. ADCMP551 16-Lead QSOP
Pin Configuration
Figure 3. ADCMP552 20-Lead QSOP
Pin Configuration
Figure 4. ADCMP553 8-Lead MSOP
Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
ADCMP551
ADCMP552
ADCMP553
3, 14
1, 4, 17, 20
VCCO
Logic Supply Terminal.
1
2
6
QA
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
2
3
5
QA
One of Two Complementary Outputs for Channel A. QA is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
4
5
2
LEA
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with LEA.
5
6
1
LEA
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with LEA.
6
7
VCCI
Input Supply Terminal.
7
8
4
INA
Inverting Analog Input of the Differential Input Stage for Channel A. The
inverting A input must be driven in conjunction with the noninverting A input.
8
9
3
+INA
Noninverting Analog Input of the Differential Input Stage for Channel A. The
noninverting A input must be driven in conjunction with the inverting A input.
10
HYSA
Programmable Hysteresis.
11
HYSB
Programmable Hysteresis.
9
12
+INB
Noninverting Analog Input of the Differential Input Stage for Channel B. The
noninverting B input must be driven in conjunction with the inverting B input.
10
13
INB
Inverting Analog Input of the Differential Input Stage for Channel B. The
inverting B input must be driven in conjunction with the noninverting B input.
11
14
8
AGND
Analog Ground.
04722-002
ADCMP551
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
VCCO
VCCI
LEA
–INB
+INB
QB
VCCO
AGND
LEB
04722-003
ADCMP552
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
VCCO
VCCI
LEA
VCCO
+INA
HYSA
–INB
QB
VCCO
AGND
LEB
VCCO
+INB
HYSB
04722-004
ADCMP553
TOP VIEW
(Not to Scale)
1
2
3
4
8
7
6
5
LEA
+INA
–INA
AGND
VCC
QA
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