参数资料
型号: EVAL-ADF4360-8EBZ1
厂商: Analog Devices Inc
文件页数: 10/24页
文件大小: 0K
描述: BOARD EVALUATION FOR ADF4360-8
标准包装: 1
主要目的: 计时,频率合成器
嵌入式:
已用 IC / 零件: ADF4360-8
主要属性: 带 VCO 的单路整数-N PLL
次要属性: 120MHz,1MHz PFD
已供物品: 板,线缆,软件
相关产品: ADF4360-8BCPZ-ND - IC SYNTHESIZER VCO 24-LFCSP
ADF4360-8BCPZRL7TR-ND - IC SYNTHESIZER VCO 24LFCSP
ADF4360-8BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP
其它名称: Q4990657
ADF4360-8
Rev. A | Page 18 of 24
Hardware Power-Up/Power-Down
If the part is powered down via the hardware (using the CE pin)
and powered up again without any change to the N counter
register during power-down, the part locks at the correct fre-
quency, because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <15 ms for 10 F capacitance. The smaller
capacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while the part is in
power-down, since the part may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the part after power-up is the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N
counter latch during power-down, the part locks at the correct
frequency, because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <15 ms for 10 F capacitance. The smaller
capacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while the part is in
power-down, because the part may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
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