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参数资料
| 型号： | EVAL-ADF4360-8EBZ1 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-8 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-8 |
| 主要属性： | 带 VCO 的单路整数-N PLL |
| 次要属性： | 120MHz，1MHz PFD |
| 已供物品： | 板，线缆，软件 |
| 相关产品： | ADF4360-8BCPZ-ND - IC SYNTHESIZER VCO 24-LFCSP ADF4360-8BCPZRL7TR-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-8BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP |
| 其它名称： | Q4990657 |
ADF4360-8
Rev. A | Page 12 of 24
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 20. To allow
the user to optimize the power dissipation vs. the output power
requirements, the tail current of the differential pair is pro-
grammable via Bits PL1 and PL2 in the control latch. Four cur-
rent levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These
levels give output power levels of 9 dBm, 6 dBm, 3 dBm,
and 0 dBm, respectively, using the correct shunt inductor to VDD
and ac coupling into a 50 load. Alternatively, both outputs can
be combined in a 1 + 1:1 transformer or a 180° microstrip cou-
pler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock, as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
VCO
RFOUTARFOUTB
BUFFER
04763-020
Figure 20. Output Stage ADF4360-8
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