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型号： EVAL-ADM2582EEB1Z
厂商： Analog Devices Inc
文件页数： 15/20页
文件大小： 0K
描述： BOARD EVAL FOR ADM2582E
标准包装： 1
系列： *
ADM2582E/ADM2587E
Rev. C | Page 4 of 20
ADM2582E TIMING SPECIFICATIONS
TA = 40°C to +85°C.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DRIVER
Maximum Data Rate
16
Mbps
Propagation Delay, Low to High
tDPLH
63
100
ns
RL = 54 Ω, CL1 = C L2 = 100 pF, see Figure 25 and Figure 29
Propagation Delay, High to Low
tDPHL
64
100
ns
RL = 54 Ω, CL1 = C L2 = 100 pF, see Figure 25 and Figure 29
Output Skew
tSKEW
1
8
ns
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 25 and Figure 29
Rise Time/Fall Time
tDR, tDF
15
ns
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 25 and Figure 29
Enable Time
tZL, tZH
120
ns
RL = 110 Ω, CL = 50 pF, see Figure 26 and Figure 31
Disable Time
tLZ, tHZ
150
ns
RL = 110 Ω, CL = 50 pF, see Figure 26 and Figure 31
RECEIVER
Propagation Delay, Low to High
tRPLH
94
110
ns
CL = 15 pF, see Figure 27 and Figure 30
Propagation Delay, High to Low
tRPHL
95
110
ns
CL = 15 pF, see Figure 27 and Figure 30
Output Skew1
tSKEW
1
12
ns
CL = 15 pF, see Figure 27 and Figure 30
Enable Time
tZL, tZH
15
ns
RL = 1 kΩ, CL = 15 pF, see Figure 28 and Figure 32
Disable Time
tLZ, tHZ
15
ns
RL = 1 kΩ, CL = 15 pF, see Figure 28 and Figure 32
1 Guaranteed by design.
ADM2587E TIMING SPECIFICATIONS
TA = 40°C to +85°C.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DRIVER
Maximum Data Rate
500
kbps
Propagation Delay, Low to High
tDPLH
250
503
700
ns
RL = 54 Ω, CL1 = C L2 = 100 pF, see Figure 25 and Figure 29
Propagation Delay, High to Low
tDPHL
250
510
700
ns
RL = 54 Ω, CL1 = C L2 = 100 pF, see Figure 25 and Figure 29
Output Skew
tSKEW
7
100
ns
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 25 and Figure 29
Rise Time/Fall Time
tDR, tDF
200
1100
ns
RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 25 and Figure 29
Enable Time
tZL, tZH
2.5
μs
RL = 110 Ω, CL = 50 pF, see Figure 26 and Figure 31
Disable Time
tLZ, tHZ
200
ns
RL = 110 Ω, CL = 50 pF, see Figure 26 and Figure 31
RECEIVER
Propagation Delay, Low to High
tRPLH
91
200
ns
CL = 15 pF, see Figure 27 and Figure 30
Propagation Delay, High to Low
tRPHL
95
200
ns
CL = 15 pF, see Figure 27 and Figure 30
Output Skew
tSKEW
4
30
ns
CL = 15 pF, see Figure 27 and Figure 30
Enable Time
tZL, tZH
15
ns
RL = 1 kΩ, CL = 15 pF, see Figure 28 and Figure 32
Disable Time
tLZ, tHZ
15
ns
RL = 1 kΩ, CL = 15 pF, see Figure 28 and Figure 32
ADM2582E/ADM2587E PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-to-Output)1
RI-O
1012
Ω
Capacitance (Input-to-Output)1
CI-O
3
pF
f = 1 MHz
Input Capacitance2
CI
4
pF
1 Device considered a 2-terminal device: short together Pin 1 to Pin 10 and short together Pin 11 to Pin 20.
2 Input capacitance is from any input data pin to ground.
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