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参数资料
| 型号： | EVAL-ADM3252EEBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADM3252E |
| 标准包装： | 1 |
| 主要目的： | 接口，隔离式，RS-232 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADM3252E |
| 主要属性： | 2.5 kV 隔离式（电源和数据）RS-232 收发器，隔离式 DC/DC 转换器 |
| 次要属性： | 2 通道 |
| 已供物品： | 板 |
ADM3252E
Data Sheet
Rev. A | Page 12 of 16
APPLICATIONS INFORMATION
PCB LAYOUT
The ADM3252E requires no external circuitry for its logic
interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 20). Bypass capacitors are
conveniently connected between Pin B1 and Pin C1 for VCC and
between Pin C10 and Pin D10 for VISO.
Figure 20. Recommended Printed Circuit Board Layout
To suppress noise and reduce ripple, a parallel combination of at
least two capacitors is recommended. The recommended capacitor
values are 0.1 μF and 10 μF for both VCC and VISO. The smaller
capacitor must have a low ESR; best practice suggests use of a
ceramic capacitor. Do not exceed 2 mm for the total lead length
between both ends of the low ESR capacitor and the input power
supply pin.
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipating into
the PCB through the ground pins. If the device is used at high
ambient temperatures, take care to provide a thermal path from
the ground pins to the PCB ground plane. The board layout in
The BGA balls are also grouped together to simplify layout and
routing. To significantly reduce the temperature inside the chip,
implement multiple vias from each of the pads to the ground
plane. The dimensions of the expanded pads are at the discre-
tion of the designer and the available board space.
In applications involving high common-mode transients,
ensure that board coupling across the isolation barrier is
minimized. Furthermore, design the board layout such that
any coupling that does occur equally affects all pins on a given
component side.
The power supply section of the ADM3252E uses a 180 MHz
oscillator frequency to pass power through its chip scale
transformers. Operation at these high frequencies may raise
concerns about radiated emissions and conducted noise. PCB
layout and construction are very important tools for controlling
radiated emissions. Refer to the AN-0971 Application Note,
Recommendations for Control of Radiated Emissions with isoPower
Devices, for extensive guidance on radiation mechanisms and
board layout considerations.
START-UP BEHAVIOR
The ADM3252E does not contain a soft start circuit. Therefore,
the start-up current and voltage behavior must be taken into
account when designing with this device.
When power is applied to VCC, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached (approximately 2.7 V). The switching circuit drives
the maximum available power to the output until it reaches the
regulation voltage, which is where PWM control begins. The
amount of current and the time required to reach regulation
voltage depends on the load and the VCC slew rate.
With a fast VCC slew rate (200 μs or less), the peak current draws
up to 100 mA/V of VCC. The input voltage goes high faster than
the output can turn on; therefore, the peak current is proportional
to the maximum input voltage.
With a slow VCC slew rate (in the millisecond range), the input
voltage is not changing quickly when VCC reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VCC is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit.
When powering up the device, do not limit the current available
may not be able to drive the output to the regulation point if a
current limiting device clamps the VCC voltage during startup.
As a result, the ADM3252E device can draw large amounts of
current at low voltage for extended periods of time.
The output voltage of the ADM3252E device exhibits VISO
overshoot to approximately 4 V during startup (see Figure 13
and Figure 14). If this overshoot could potentially damage compo-
nents attached to VISO, a voltage limiting device, such as a Zener
diode, can be used to clamp the voltage.
10
515-
007
A
B
C
D
E
F
G
3
24
15
7
68
10
911
H
J
K
L
C3
C1
C2
C4
A1 BALL
CORNER
VIA TO GNDISO
0.1F
ADM3252E
TOP VIEW
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