参数资料
| 型号： | EVAL-AVB-LISTENER |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | EVAL-AVB-LISTENER ADV7612 |
| 标准包装： | 1 |
| 系列： | * |
ADV7612
Timing Diagrams
Data Sheet
SDA
SCL
t 3
t 6
t 1
t 5
t 3
t 2
t 7
t 4
t 8
Figure 3. I C Timing
2
t 9
t 10
LLC
t 11
t 12
P0 TO P23, HS,
VS/FIELD/ALSB, DE
Figure 4. Pixel Port and Control SDR Output Timing
t 15
SCLK
t 16
t 17
LRCLK
t 18
I 2 S
LEFT-JUSTIFIED
t 19
MODE
MSB
t 20
MSB – 1
t 19
I 2 S
I 2 S MODE
I 2 S
RIGHT-JUSTIFIED
MSB
t 20
MSB – 1
t 19
NOTES
MODE
MSB
t 20
LSB
1. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.
2. I 2 S SIGNALS ARE ACCESSIBLE VIA THE AP1 TO AP4 PINS.
Figure 5. I 2 S Timing
Rev. E | Page 6 of 20
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