参数资料
| 型号： | EX64-TQG64I |
| 厂商： | Microsemi SoC |
| 文件页数： | 2/48页 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 64-TQFP |
| 标准包装： | 160 |
| 系列： | EX |
| 逻辑元件/单元数： | 128 |
| 输入/输出数： | 41 |
| 门数： | 3000 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
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eX FPGA Architecture and Characteristics
1-6
Revision 10
Table 1-2 describes the I/O features of eX devices. For more information on I/Os, refer to Microsemi eX,
SX-A, and RT54SX-S I/Os application note.
The eX family supports mixed-voltage operation and is designed to tolerate 5.0 V inputs in each case.
A detailed description of the I/O pins in eX devices can be found in "Pin Description" on page 1-31.
Hot-Swapping
eX I/Os are configured to be hot-swappable. During power-up/down (or partial up/down), all I/Os are
tristated, provided VCCA ramps up within a diode drop of VCCI. VCCA and VCCI do not have to be stable.
during power-up/down, and they do not require a specific power-up or power-down sequence in order to
avoid damage to the eX devices. In addition, all outputs can be programmed to have a weak resistor pull-
up or pull-down for output tristate at power-up. After the eX device is plugged into an electrically active
system, the device will not degrade the reliability of or cause damage to the host system. The device's
output pins are driven to a high impedance state until normal chip operating conditions are reached.
Please see the application note, Microsemi SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications, which also applies to the eX devices, for more information on hot swapping.
Power Requirements
Power consumption is extremely low for the eX family due to the low capacitance of the antifuse
interconnects. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or
EPROM), making it the lowest-power FPGA architecture available today.
Low Power Mode
The eX family has been designed with a Low Power Mode. This feature, activated with setting the special
LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of the device is turned off and the device
consumes minimal power with low standby current. In addition, all input buffers are turned off, and all
outputs and bidirectional buffers are tristated when the device enters this mode. Since the core of the
device is turned off, the states of the registers are lost. The device must be re-initialized when returning
to normal operating mode. I/Os can be driven during LP mode. For details, refer to the Design for Low
Power in Microsemi Antifuse FPGAs application note under the section Using the LP Mode Pin on eX
Devices. Clock pins should be driven either HIGH or LOW and should not float; otherwise, they will draw
current and burn power. The device must be re-initialized when exiting LP mode.
Table 1-2 I/O Features
Function
Description
Input
Buffer
Threshold
Selection
5.0V TTL
3.3V LVTTL
2.5V LVCMOS2
Nominal Output Drive
5.0V TTL/CMOS
3.3V LVTTL
2.5V LVCMOS 2
Output Buffer
“Hot-Swap” Capability
I/O on an unpowered device does not sink current
Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power-Up
Individually selectable pull ups and pull downs during power-up (default is to power up in
tristate)
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
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