参数资料
型号: EZLC-4421 HB
厂商: Silicon Laboratories Inc
文件页数: 19/45页
文件大小: 0K
描述: KIT EZLINK F930/SI4421 HIGH BAND
标准包装: 1
Si4421
Bits 4-3 (g1 to g0) :
LNA gain select:
Bits 2-0 (r2 to r0) :
g1
0
0
1
1
RSSI detector threshold:
g0
0
1
0
1
Gain relative to maximum [dB]
0
-6
-14
-20
r2
0
0
0
0
1
1
1
1
r1
0
0
1
1
0
0
1
1
r0
0
1
0
1
0
1
0
1
RSSI setth
-103
-97
-91
-85
-79
-73
Reserved
Reserved
The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
RSSI th =RSSI setth +G LNA
6. Data Filter Command
Bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
al
6
ml
5
1
4
s
3
1
2
f2
1
f1
0
f0
POR
C22Ch
Bit 7 ( al ): Clock recovery (CR) auto lock control
1: auto mode: the CR starts in fast mode, after locking it switches to slow mode. Bit 6 ( ml ) has no effect.
0: manual mode, the clock recovery mode is set by Bit 6 ( ml )
Bit 6 ( ml ): Clock recovery lock control
1: fast mode, fast attack and fast release (4 to 8-bit preamble (1010...) is recommended)
0: slow mode, slow attack and slow release (12 to 16-bit preamble is recommended)
Using the slow mode requires more accurate bit timing (see Data Rate Command , page 17).
Bit 4 ( s ):
Select the type of the data filter:
s
0
1
Filter Type
Digital filter
Analog RC filter
Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time
constant is automatically adjusted to the bit rate defined by the Data Rate Command (page 17).
Note: Bit rate cannot exceed 115 kpbs in this mode.
Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set
by the external capacitor connected to this pin and VSS.
The table shows the optimal filter capacitor values for different data rates
Data Rate [kbps]
Filter Capacitor Value
1.2
12 nF
2.4
8.2 nF
4.8
6.8 nF
9.6
3.3 nF
19.2
1.5 nF
38.4
680 pF
57.6
270 pF
115.2
150 pF
256
100 pF
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO cannot be used.
19
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