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参数资料
| 型号： | FA3686V |
| 厂商： | FUJI ELECTRIC CO LTD |
| 元件分类： | 稳压器 |
| 英文描述： | 0.4 A DUAL SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | 1.10 MM HEIGHT, TSSOP-16 |
| 文件页数： | 4/18页 |
| 文件大小： | 389K |
| 代理商： | FA3686V |
FA3686V
12
s Description of each circuit
1. Reference voltage circuit (VREF)
This circuit generates the reference voltage of 1.00V (ch1: ±1%;
ch2, 3: ±2%) compensated in temperature from VCC voltage,
and is connected to the non-inverting input of the error amplifier.
This voltage cannot be observed directly because an external
pin for this purpose is not provided.
2. Regulated voltage circuit (VREG)
This circuit generates 2.20V±1% based on the reference
voltage VREF, and is used as the power supply of the internal IC
circuits. This voltage is generated when the supply voltage,
VCC, is input. The VREG voltage also is used as a regulated
power supply for soft start and others. The output current for
external circuit should be within 1mA. A capacitor connected
between VREG pin and GND pin is necessary to stable the
VREF voltage (To determine capacitance, refer to recommended
operating conditions). The VREG voltage is regulated in VCC
voltage of 2.4V or above.
3. Oscillator
The oscillator generates a triangular waveform by charging and
discharging the built-in capacitor. A desired oscillation
frequency can be set by the value of the resistor connected to
the RT pin (Fig. 1). The built-in capacitor voltage oscillates
between approximately 0.82V and 1.38V at fosc=500kHz (that
of ch1 and ch2 are slightly different) with almost the same
charging and discharging gradients (Fig. 2). You can set the
desired oscillation frequency by changing the gradients using
the resistor connected to the RT pin. (Large RT: low frequency,
small RT: high frequency) The oscillator waveform cannot be
observed from the outside because a pin for this purpose is not
provided. The RT pin voltage is approximately 1V DC in normal
operation. The oscillator output is connected to the PWM
comparator.
4. Error amplifier circuit
The error amplifiers 1, 2, 3 have inverting input pins of IN1– pin
(Pin 14), IN2– pin (Pin 4) and IN3– pin (Pin 2). The non-inverting
input is internally connected to the reference voltage VREF of the
error amplifier 1 (1.00V±1%; 25C) and the error amplifiers 2, 3
(1.00V±2%; 25C). The FB pins (Pin1, Pin15) are the output of
the error amplifiers. An external RC network is connected
between FB pin and IN– pin for gain and phase compensation
setting. The error amplifier 3 can be used for a series regulator.
Fig. 1
Fig. 2
12
OSC
RT
RT value: small
RT value: large
0.82V
1.38V
+
14
15
3
13
IN1-
VREG
IN2-
FB2
FB1
Comp
Vout1
Vout2
RNF1
RNF2
VREF
(1.0V)
R1
R2
R3
R4
4
2
1
R5
R6
RNF3
FB3
Er.Amp.1
Er.Amp.2
Er.Amp.3
IN3-
Vout3
Fig. 3
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