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参数资料
| 型号： | FA3686V |
| 厂商： | FUJI ELECTRIC CO LTD |
| 元件分类： | 稳压器 |
| 英文描述： | 0.4 A DUAL SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | 1.10 MM HEIGHT, TSSOP-16 |
| 文件页数： | 7/18页 |
| 文件大小： | 389K |
| 代理商： | FA3686V |
FA3686V
15
10. PGS circuit
The PGS pin is an open drain output of Nch MOSFET for
transmitting fault signals of the power supply. The PGS circuit is
enabled when Vcc voltage is over the operating threshold
voltage (approximately 1V). The Nch MOSFET turns ON and
the PGS pin is connected to GND if any of the following three
conditions occurs:
1) the VCC voltage is below the threshold voltage (VCC
increasing: 2.35V typ.; VCC decreasing: 2.25V typ.), 2) UVLO
turns on (VCC=2.1V or below), 3) IC is off latch mode.
The operation sequence is shown in Fig. 8.
As shown in Fig. 8, in the case of increasing the Vcc voltage
with the voltage V applied to the PGS pin, when the Vcc voltage
reaches 1V, PGS circuit is enabled and detects that the Vcc
voltage is not enough high. Then PGS circuit turns the Nch
MOSFET on and output fault signal. The fault signal is
cancelled when the VCC voltage exceeds 2.35V (typ.).
In the case that the VCC voltage exceeds 2.53V (typ.) and the
IC is off latch mode, the PSG circuit detects it as abnormal and
the Nch MOSFET is turned on.
In the case of decreasing the VCC voltage, the circuit sends out
fault signals when the VCC voltage is below 2.25V (typ.) and
continues to output until the VCC voltage reaches below the
PGS circuit operation threshold voltage of approximately 1V.
(Under the VCC voltage of 1V, the circuit does not operate
normally.)
Fig. 8
+
5
PGS
11
V
UVLO
VPGS
Timer latch
VCC decreasing
VCC increasing
1V
VPGS voltage 2.25V
Hysteresis voltage
PGS
pin
voltage
Vcc voltage stable state
Off latch mode
Off latch mode reset
PGS operation
Vcc
V
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