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参数资料
| 型号： | FA3687V |
| 厂商： | FUJI ELECTRIC CO LTD |
| 元件分类： | 稳压器 |
| 英文描述： | 0.4 A DUAL SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | 1.10 MM HEIGHT, TSSOP-16 |
| 文件页数： | 4/18页 |
| 文件大小： | 378K |
| 代理商： | FA3687V |
FA3687V
12
s Description of each circuit
1. Reference voltage circuit (VREF)
This circuit generates the reference voltage of 1.00V±1%
compensated in temperature from VCC voltage, and is
connected to the non-inverting input of the error amplifier. The
voltage cannot be observed directly because there is no
external pin for this purpose.
2. Regulated voltage circuit (VREG)
This circuit generates 2.20V±1% based on the reference
voltage VREF, and is used as the power supply of the internal IC
circuits. The voltage is generated when the supply voltage, VCC
is input. The VREG voltage is also used as a regulated power
supply for soft start, maximum duty cycle limitation, and others.
The output current for external circuit should be within 1mA. A
capacitor connected between VREG pin and GND pin is
necessary to stabilize the VREG voltage (To determine
capacitance, refer to recommended operating conditions). The
VREG voltage is regulated in VCC voltage of 2.4V or above.
3. Oscillator
The oscillator generates a triangular waveform by charging and
discharging the built-in capacitor. A desired oscillation
frequency can be set by the value of the resistor connected to
the RT pin (Fig. 1). The built-in capacitor voltage oscillates
between approximately 0.82V and 1.38V at fosc=500kHz (that
of ch1 and ch2 are slightly different) with almost the same
charging and discharging gradients (Fig. 2).
You can set the desired oscillation frequency by changing the
gradients using the resistor connected to the RT pin (Large RT:
Low frequency, Small RT: High frequency). The oscillator
waveform cannot be observed from the outside because a pin
for this purpose is not provided. The RT pin voltage is
approximately 1V DC in normal operation. The oscillator output
is connected to the PWM comparator.
4. Error amplifier circuit
The error amplifier 1 has the inverting input of IN1(–) pin
(Pin14). The non-inverting input is internally connected to the
reference voltage VREF (1.00V±1%; 25C). The error amplifier 2
has the inverting input IN2(–) pin (Pin4) and non-inverting input
IN2(+) pin (Pin5) externally. Since each input of error amplifier
2 is connected to the pins, CH2 is suitable for any circuit
topology. The FB pins (Pin3, Pin15) are the output of the error
amplifier. An external RC network is connected between FB pin
and IN–pin for gain and phase compensation setting. (Fig. 3)
For connecting of each topology, see “Design advice”.
Fig. 1
Fig. 2
Fig. 3
12
OSC
RT
RT value:Small
RT value:Large
0.82V
1.38V
+
14
15
5
4
3
13
IN1-
VREG
IN2+
IN2-
FB2
FB1
Comp
Vout1
Vout2
RNF1
RNF2
VREF
(1.0V)
R1
R2
R3
R4
R5
R6
Er. Amp.1
Er. Amp.2
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