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| 型号： | FA3687V |
| 厂商： | FUJI ELECTRIC CO LTD |
| 元件分类： | 稳压器 |
| 英文描述： | 0.4 A DUAL SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | 1.10 MM HEIGHT, TSSOP-16 |
| 文件页数： | 8/18页 |
| 文件大小： | 378K |
| 代理商： | FA3687V |
FA3687V
16
4. Setting maximum duty cycle
As described in the Fig. 9, you can limit maximum duty cycle by
connecting a resistor divider “R7, R8 or R9, R10” between CS1,
CS2 and VREG pin. Set the maximum duty cycle considering
that relation between the maximum output duty cycle and the
CS pin voltage changes with operation frequency as described
in the characteristic curves of “Output duty cycle vs. oscillation
frequency” and “Output duty cycle vs. CS voltage”. When the
maximum duty cycle is limited, CS pin voltage at start-up is
described in Fig. 10, and the approximate value of soft start
period can be obtained by the following expressions:
The divided CS1 voltage is obtained by:
The divided CS2 voltage is obtained by:
VCS1n and VCS2n are the voltages of CS1 and CS2 under a
certain output duty cycle and varies with operation frequencies.
The values of VCS1n and VCS2n can be obtained from the
characteristic curves of “Output duty cycle vs. CS voltage”.
The charging of CCS1 and CCS2 after UVLO is unlocked.
Therefore, the period from power-on of Vcc to widening n% of
output duty cycle is the sum of t0 and t.
5. Determining the output voltage of DC-DC converters
The ways to determine the output voltage of the DC-DC
converter of each channel is shown in Fig. 10 and the following
equations.
For ch1:
The positive output voltage of DC-to-DC converter (a buck, a
boost) is determined by:
For ch2:
The positive output voltage of DC-to-DC converter is
determined by:
Here,
When R5=R6,
CCS1, CCS2:
Capacitance connected to the CS1 or CS2 pin [F]
R7, R8, R9, R10: Resistance connected to CS1 or CS2 pin [k
]
VCS1 =
R8
VREG
R7 + R8
VCS2 =
R9
VREG
R9 + R10
For CS2
()
t [ms] = R0
CCS2
1n
VCS2n – VCS2
VREG – VCS2
Vout1 =
R1 + R2
VREF
R2
Vout2 = V1
R3 + R4
R3
V1 = VREG
R6
R5 + R6
For CS1
()
t [ms] = R0
CCS1
1n 1–
VCS1n
VCS1
()
Vout2 = VREG
R3 + R4
2R3
13
10
VREG
CS1
CCS1
R7
R8
13
7
CS2
VREG
R9
R10
CCS2
Fig. 9
Threshold voltage
Vcc
t
t0
t
t0
VREG
VCS1N
R8
R7+R8
Threshold voltage
t0: Time from power-on of VCC to reaching unlock voltage of UVLO.
VREG
VREG pin voltage
VCS2n
VCC
R9
R9+R10
Fig. 10
Ch1
Ch2
R0 =
R7 R8
R7+R8
R0 =
R9 R10
R9+R10
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