参数资料
型号: FAN2106EMPX
厂商: Fairchild Semiconductor
文件页数: 10/15页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 6A 25MLP
标准包装: 1
系列: TinyBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 3 V ~ 21 V
输入电压: 3 V ~ 24 V
PWM 型: 电流模式
频率 - 开关: 300kHz ~ 600kHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 25-MLP
包装: 标准包装
供应商设备封装: 25-MLP(5x6)
产品目录页面: 1220 (CN2011-ZH PDF)
配用: FEB167-ND - BOARD EVAL FOR FAN2106
其它名称: FAN2106EMPXDKR
Circuit Description
PWM Generation
Soft-start time is a function of switching frequency.
Refer to Figure 2 for the PWM control mechanism.
FAN2106 uses the summing-mode method of control to
generate the PWM pulses. An amplified current-sense
EN
1.35V
signal is summed with an internally generated ramp and
the combined signal is compared with the output of the
2400 CLKs
0.8V
error amplifier to generate the pulsewidth to drive the
high-side MOSFET. Sensed current from the previous
cycle is used to modulate the output of the summing
FB
Fault
block. The output of the summing block is also
compared against a voltage threshold set by the R LIM
resistor to limit the inductor current on a cycle-by-cycle
basis. The R RAMP resistor helps set the charging current
for the internal ramp and provides input voltage feed-
SS
1.0V
0.8V
Latch
Enable
forward function. The controller facilitates external
compensation for enhanced flexibility.
Initialization
Once V CC exceeds the UVLO threshold and EN is HIGH,
the IC checks for a shorted FB pin before releasing the
internal soft-start ramp (SS).
If the parallel combination of R1 and R BIAS is ≤ 1 K Ω , the
internal SS ramp is not released and the regulator does
not start.
Enable
FAN2106 has an internal pull-up to the ENABLE (EN)
pin so that the IC is enabled once V CC exceeds the
UVLO threshold. Connecting a small capacitor across
EN and AGND delays the rate of voltage rise on the EN
pin. The EN pin also serves for the restart whenever a
fault occurs (refer to the Auto-Restart section) . If the
regulator is enabled externally, the external EN signal
should go HIGH only after V CC is established. For
applications where such sequencing is required,
FAN2106 can be enabled (after the V CC comes up) with
external control, as shown in Figure 21.
Figure 21. Enabling with External Control
Soft-Start
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), the fault latch is inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply V IN before V CC reaches its UVLO threshold. Normal
sequence for powering up would be VIN ? VCC ? EN.
? 2009 Fairchild Semiconductor Corporation
FAN2106 ? Rev. 1.1.2
10
3200 CLKs
T0.8
4000 CLKs
T1.0
Figure 22. Soft-Start Timing Diagram
Cycling V CC or the EN pin discharges the internal SS
and resets the IC. In applications where external EN
signal is used, V IN and V CC should be established before
the EN signal comes up to prevent skipping the soft-
start function.
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until
internal SS ramp reaches 95% of V REF (~0.76 V). This
helps the regulator start on a pre-biased output and
ensures that the pre-biased outputs are not discharged
during soft-start.
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, under-
voltage, and over-temperature conditions.
Under-Voltage Shutdown
If the voltage on the FB pin remains below the under-
voltage threshold for 16 consecutive clock cycles, the
fault latch is set and the converter shuts down. This
protection is not active until the internal SS ramp
reaches 1.0 V during soft-start.
Over-Voltage Protection
If voltage on the FB pin exceeds 115% of V REF for two
consecutive clock cycles, the fault latch is set and
shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
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