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参数资料
| 型号： | FAN3229TMPX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 20/26页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR LOW DUAL 2A HS 8MLP |
| 标准包装： | 1 |
| 配置： | 低端 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 19ns |
| 电流 - 峰： | 3A |
| 配置数： | 2 |
| 输出数： | 2 |
| 电源电压： | 4.5 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-MLP |
| 供应商设备封装： | 8-MLP（3x3） |
| 包装： | 标准包装 |
| 产品目录页面： | 1215 (CN2011-ZH PDF) |
| 其它名称： | FAN3229TMPXDKR |
Truth Table of Logic Operation
The FAN3228/FAN3229 truth table indicates the
operational states using the dual-input configuration. In
a non-inverting driver configuration, the IN- pin should
be a logic low signal. If the IN- pin is connected to logic
high, a disable function is realized, and the driver output
remains low regardless of the state of the IN+ pin.
Operational Waveforms
At power-up, the driver output remains low until the V DD
voltage reaches the turn-on threshold. The magnitude of
the OUT pulses rises with V DD until steady-state V DD is
reached. The non-inverting operation illustrated in
Figure 53 shows that the output remains low until the
UVLO threshold is reached, the output is in-phase with
IN+
0
0
1
1
IN-
0
1
0
1
OUT
0
0
1
0
the input.
In the non-inverting driver configuration in Figure 51, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
high to disable the driver and the output remains low,
regardless of the state of the IN+ pin.
VDD
PWM
IN+
IN-
FAN3228/9
OUT
Figure 53. Non-Inverting Startup Waveforms
GND
Figure 51. Dual-Input Driver Enabled,
For the inverting configuration of Figure 52, startup
waveforms are shown in Figure 54. With IN+ tied to V DD
and the input signal applied to IN–, the OUT pulses are
inverted with respect to the input. At power-up, the
inverted output remains low until the V DD voltage
reaches the turn-on threshold, then it follows the input
with inverted phase.
Non-Inverting Configuration
In the inverting driver application in Figure 52, the IN+
pin is tied high. Pulling the IN+ pin to GND forces the
output low, regardless of the state of the IN- pin.
Figure 52. Dual-Input Driver Enabled,
Inverting Configuration
Figure 54. Inverting Startup Waveforms
? 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 ? Rev. 1.1.0
20
www.fairchildsemi.com
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