参数资料
型号: FAN5026MTC
厂商: Fairchild Semiconductor
文件页数: 4/17页
文件大小: 0K
描述: IC CONTROLLER DDR 28TSSOP
产品变化通告: Mold Compound Change 30/Nov/2007
标准包装: 49
应用: 控制器,DDR
输入电压: 3 V ~ 16 V
输出数: 2
输出电压: 0.9 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
其它名称: FAN5026MTC_NL
FAN5026MTC_NL-ND
Pin Definitions
Pin #
11
12
17
13
14
15
Name
ILIM1
SS1
SS2
DDR
VIN
PG1
Description
Current Limit 1 . A resistor from this pin to GND sets the current limit.
Soft Start . A capacitor from this pin to GND programs the slew rate of the converter during
initialization. During initialization, this pin is charged with a 5mA current source.
DDR Mode Control . HIGH = DDR Mode. LOW = two separate regulators operating 180
degrees out of phase.
Input Voltage . Normally connected to the battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100K ? resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
Power-Good Flag . An open-drain output that pulls LOW when V SEN is outside a ±10% range of
the 0.9V reference.
Power-Good 2 . When not in DDR Mode, open-drain output that pulls LOW when the V OUT is
PG2 /
16
out of regulation or in a fault condition.
REF2OUT Reference Out 2 . When in DDR Mode, provides a buffered output of REF2. Typically used as
the V DDQ/2 reference.
18
28
ILIM2 /
REF2
VCC
Current Limit 2 . When not in DDR Mode, a resistor from this pin to GND sets the current limit.
Reference for reg #2 when in DDR Mode. Typically set to V OUT1/2 .
VCC . This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
Block Diagram
Figure 4. IC Block Diagram
? 2005 Fairchild Semiconductor Corporation
FAN5026 ? Rev. 1.0.8
4
www.fairchildsemi.com
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