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参数资料
| 型号： | FAN6208MY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR SR SYNC RECT LLC 8-SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 输入电压： | 9.3 V ~ 28 V |
| 输出电压： | 12V |
| 功率（瓦特）： | 1W |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOP |
| 包装： | 带卷 (TR) |
Electrical Characteristics
V DD =20 V, T A =25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Gate Section
V Z1 V Z2
Gate Output Voltage
Maximum (Clamping)
V DD =20 V
10
12
14
V
V OL1 V OL2
V OH1 V OH2
Gate Output Voltage LOW
Gate Output Voltage HIGH
V DD =12 V; I O =100 mA
V DD =12 V; I O =100 mA
9
0.5
V
V
t R1 t R2
t F1 t F2
t PD_HIGH_DETL1
t PD_HIGH_DETL2
t PD_LOW_ DETL1
t PD_LOW_ DETL2
t ON_MAX1
t ON_MAX2
t INHIBIT_LF1
t INHIBIT_LF2
t INHIBIT_HF1
t INHIBIT_HF2
Rising Time
Falling Time
Propagation Delay to Gate
Output HIGH (DETL
Trigger)
Propagation Delay to Gate
Output LOW (DETL
Trigger)
Maximum On-Time
Gate Inhibit Time (from
Turn-Off to Next Turn-On)
Gate Inhibit Time (from
Turn-Off to Next Turn-On)
V DD =12 V; C L =6 nF;
V GATE =2 V to 9 V
V DD =12 V; C L =6 nF;
V GATE =9 V to 2 V
t R : 0 V~2 V, V DD =12 V
(DET Floating)
t F : 100%~90%, V DD =12 V
(DET Floating)
Trim Maximum On-Time
V RP < 1.5 V
V RP > 1.5 V
30
30
9.0
1.8
1.25
70
50
120
120
10.5
2.1
1.45
120
70
12.0
2.5
1.70
ns
ns
ns
ns
μs
μs
μs
t BLANKING1
t BLANKING2
Blanking Time for SR Turn-
Off Triggered by DETL
High (Minimum On-Time)
300
ns
Gate ON-Time Increase
K R
Rate Between Two
t ON (n) / t ON (n-1) %
140
%
Consecutive Cycles
Timing Estimator Section
Detection Window for
t DW
Insufficient Dead Time
(from Gate Turn-Off to
80
125
150
ns
DETL HIGH)
t SHRINK-DT
t DEAD
Gate Shrink Time by
Insufficienct Dead Time
Dead Time by Timing
Estimator (70 kHz ~
140 kHz, V RP < 1.5 V)
Dead Time by Timing
Estimator (160kHz ~
240 kHz, V RP > 1.5V)
R RP =20 K ? , t DETL =5 μs
t DETL =4 μs , R RP =20 K ?
t DETL =6 μs , R RP =20 K ?
t DETL =2.5 μs , R RP =43 K ?
t DETL =3.8 μs , R RP =43 K ?
1.00
210
570
220
560
1.25
300
720
320
670
1.50
390
870
420
780
μs
ns
DETL HIGH-to-LOW
t DB
Debounce Time for Gate
150
ns
Turn-on Trigger
t SHRINK-RNG
Gate Shrink by DETL
Ringing around Zero
1.2
μs
t Green_DH
DETL Pull-HIGH Time
Threshold for Green Mode
18
24
30
μs
Continued on the following page…
? 2010 Fairchild Semiconductor Corporation
FAN6208 ? Rev. 1.0.4
6
www.fairchildsemi.com
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