参数资料
型号: FAN6555MX
英文描述: SMPS Controller
中文描述: 开关电源控制器
文件页数: 5/12页
文件大小: 91K
代理商: FAN6555MX
PRODUCT SPECIFICATION
FAN6555
REV. 1.1.2 1/9/02
5
Applications
Using the FAN6555 for DDR Bus Termination
The circuit schematic in Figure 1 shows a recommended
approach for constructing a bus terminating solution for a
DDR bus. This circuit can be used in PC memory and Graph-
ics memory applications as shown in Figures 3 and 4. Note
that the FAN6555 can provide the voltage reference (V
REF
)
and terminating voltages (V
TT
). Using the layout
as shown in Figures 5, 6, and 7, and measuring the V
TT
performance using the test setup as described in Figure 8,
the FAN6555 delivered a V
TT
± 20mV for 1A to 2A loads
(see Figure 9). Table 1 provides a recommended parts list.
An alternate application circuit for the FAN6555 is shown in
Figure 2. The number of external components is reduced
compared to the circuit in Figure 1. This is achieved by
replacing four, 0.1μF bypass capacitors with one, low ESR,
10μF ceramic capacitor placed right next to U1. Two 100
resistors are also eliminated. High value, surface-mount
MLC capacitors were not available when the original appli-
cation circuit (Figure 1) was developed. Both application
circuits offer the same electrical performance but the circuit
shown in Figure 2 has a reduced bill-of-materials. Table 2
shows the recommended parts list for the circuit of Figure 2.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination V
REF
& V
TT
requirements. The FAN6555 can be used for those
applications.
Figure 2. Alternate Application Circuit
16
15
14
13
12
11
10
9
U1
FAN6555
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
1
2
3
4
5
6
7
8
R3
100k
VCCQ
VREFOUT
VTT
2.5V TO 4V
SHDN
VREFIN
GND
GND
TO SDRAMS
C4 1nF
C5
470
μ
F
R1 100k
R2 1k
C2
0.1
μ
F
C1
820
μ
F
F2V
OS-CON
L1 3.3
μ
H
C3 10
μ
F
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