参数资料
型号: FAN73832MX_WS
厂商: Fairchild Semiconductor
文件页数: 13/16页
文件大小: 0K
描述: IC GATE DRIVER HI/LOW SIDE 8SOIC
标准包装: 3,000
配置: 半桥
输入类型: 非反相
延迟时间: 580ns
电流 - 峰: 350mA
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 600V
电源电压: 15 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOP
包装: 带卷 (TR)
Typical Application Information
1. Normal Operating Consideration
The FAN73832 is a single PWM input, half-bridge, gate-
drive IC with programmable dead-time and shutdown
functions.
The dead-time is set with a resistor (R DT ) at the DT/SD
pin. The wide dead-time programming range provides
the flexibility to optimize drive signal timing for a
selection of switching devices (MOSFET or IGBT) and
applications.
The turn-on time delay circuitry (Dead-Time)
accommodates resistor values from 20k Ω to 200k Ω with
a dead-time proportional to the R DT resistance.
If the DT/SD pin voltage decreases below 1.2V in the
normal operation, the IC enters shutdown mode.
The external dead-time setting resistor (R DT ) is at least
above 20K Ω for normal operation in typical applications.
2. Under-Voltage Lockout (UVLO)
The FAN73832 has an under-voltage lockout (UVLO)
protection circuit for high- and low-side channels to
prevent malfunction when V DD and V BS are lower than
the specified threshold voltage. The UVLO circuitry
monitors the supply voltage (V DD ) and bootstrap
capacitor voltage (V BS ) antepenult.
? 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.2
13
3. Layout Consideration
For optimum performance of the high- and low-side gate
drivers, considerations must be taken during printed
circuit board (PCB) layout.
3.1 Supply Capacitors
If the output stages are able to quickly turn-on a
switching device with a high value of current, the supply
capacitors must be placed as close as possible to the
device pins (V DD and GND for the ground-tied supply, V B
and V S for the floating supply) to minimize parasitic
inductance and resistance.
3.2 Gate Drive Loop
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/emis-
sion and improve the power switch turn-on and off per-
formances, gate drive loops must be reduced as much
as possible.
3.3 Ground Plane
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
www.fairchildsemi.com
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