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参数资料
| 型号： | FDD3680 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V 25A D-PAK |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 标准包装： | 2,500 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 25A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 46 毫欧 @ 6.1A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 53nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 1735pF @ 50V |
| 功率 - 最大： | 1.6W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252 |
| 包装： | 带卷 (TR) |
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ Max
Units
Drain-Source Avalanche Ratings
(Note 1)
W DSS
Single Pulse Drain-Source
V DD = 50 V,
I D = 6.1 A
245
mJ
Avalanche Energy
I AR
Maximum Drain-Source
6.1
A
Avalanche Current
Off Characteristics
BV DSS
Drain–Source Breakdown
Voltage
V GS = 0 V,
I D = 250 μ A
100
V
? BV DSS
? T J
I DSS
Breakdown Voltage Temperature I D = 250 μ A, Referenced to 25 ° C
Coefficient
Zero Gate Voltage Drain Current V DS = 80 V, V GS = 0 V
–101
10
mV/ ° C
μ A
I GSSF
I GSSR
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V GS = 20 V,
V GS = –20 V
V DS = 0 V
V DS = 0 V
100
–100
nA
nA
On Characteristics
(Note 2)
V GS(th)
Gate Threshold Voltage
V DS = V GS ,
I D = 250 μ A
2
2.4
4
V
? V GS(th )
? T J
Gate Threshold Voltage
Temperature Coefficient
I D = 250 μ A, Referenced to 25 ° C
–6.5
mV/ ° C
R DS(on)
I D(on)
g FS
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
V GS = 10 V,
V GS = 10 V,
V GS = 6 V,
V GS = 10 V,
V DS = 5 V,
I D = 6.1 A
I D = 6.1 A, T J = 125 ° C
I D = 5.8 A
V DS = 5 V
I D = 6.1 A
25
32
61
34
25
46
92
51
m ?
A
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = 50 V,
f = 1.0 MHz
V GS = 0 V,
1735
176
53
pF
pF
pF
Switching Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
V DD = 50 V,
V GS = 10 V,
V DS = 50 V,
V GS = 10 V
I D = 1 A,
R GEN = 10 ?
I D = 6.1 A,
14
8.5
63
21
38
8.1
25
17
94
34
53
ns
ns
ns
ns
nC
nC
Q gd
Gate–Drain Charge
9.2
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
2.9
A
V SD
Drain–Source Diode Forward
Voltage
V GS = 0 V,
I S = 2.9 A (Note 2)
0.73
1.3
V
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
b) R θ JA = 96 oC/W on a
a) R θ JA = 40oC/ W when
minimum mounting pad.
mounted on a 1in2 pad of
2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
FDD3680 Rev B1(W)
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