参数资料
型号: FDD86250
厂商: Fairchild Semiconductor
文件页数: 2/6页
文件大小: 0K
描述: MOSFET N-CH 150V 8A DPAK
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 150V
电流 - 连续漏极(Id) @ 25° C: 8A
开态Rds(最大)@ Id, Vgs @ 25° C: 22 毫欧 @ 8A,10V
Id 时的 Vgs(th)(最大): 4V @ 250µA
闸电荷(Qg) @ Vgs: 33nC @ 10V
输入电容 (Ciss) @ Vds: 2110pF @ 75V
功率 - 最大: 3.1W
安装类型: 表面贴装
封装/外壳: TO-252-3,DPak(2 引线+接片),SC-63
供应商设备封装: TO-252,(D-Pak)
包装: 标准包装
其它名称: FDD86250DKR
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DSS
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 120 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
150
106
1
±100
V
mV/°C
μ A
nA
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
2.0
2.9
-10
4.0
V
mV/°C
V GS = 10 V, I D = 8 A
18.4
22
r DS(on)
Static Drain to Source On Resistance
V GS = 6 V, I D = 6.5 A
21.4
31
m Ω
V GS = 10 V, I D = 8 A, T J = 125 °C
35.8
45
g FS
Forward Transconductance
V DS = 10 V, I D = 8 A
28
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 75 V, V GS = 0 V,
f = 1 MHz
1585
167
7
0.6
2110
225
15
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
11.2
20
ns
t r
t d(off)
t f
Q g
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
V DD = 75 V, I D = 8 A,
V GS = 10 V, R GEN = 6 Ω
V GS = 0 V to 10 V
3.7
20
4
23
10
32
10
33
ns
ns
ns
nC
Q g
Q gs
Total Gate Charge
Gate to Source Charge
V GS = 0 V to 5 V
V DD = 75 V,
I D = 8 A
12.8
6.7
18
nC
nC
Q gd
Gate to Drain “Miller” Charge
4.7
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source-Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = 8 A
V GS = 0 V, I S = 2.6 A
I F = 8 A, di/dt = 100 A/ μ s
(Note 2)
(Note 2)
0.78
0.73
71
104
1.3
1.2
113
166
V
ns
nC
Notes :
1: R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
a) 40 °C/W when mounted on a
1 in 2 pad of 2 oz copper
2: Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3: Starting T J = 25 ° C, L = 1.0 mH, I AS = 19 A, V DD = 135 V, V GS = 10 V.
b) 96 °C/W when mounted on
a minimum pad
?2010 Fairchild Semiconductor Corporation
FDD86250 Rev.C1
2
www.fairchildsemi.com
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