参数资料
型号: FDMF6704A
厂商: Fairchild Semiconductor
文件页数: 5/14页
文件大小: 0K
描述: MODULE DRMOS XS 40-MLP
标准包装: 1
系列: XS™ DrMOS
类型: 高端/低端驱动器
输入类型: 非反相
输出数: 1
电流 - 输出 / 通道: 35A
电流 - 峰值输出: 80A
电源电压: 3 V ~ 14 V
工作温度: -55°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 40-MLP
供应商设备封装: 40-MLP(6x6)
包装: 标准包装
其它名称: FDMF6704ADKR
Description of Operation
Circuit Description
The FDMF6704A is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 1 MHz.
Low-Side Driver
The low-side driver (GL) is designed to drive a ground
referenced low R DS(ON) N-channel MOSFET. The bias for GL is
internally connected between VDRV and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB = 0 V), GL is
held low.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal diode and external bootstrap capacitor (C BOOT ). During
start-up, VSWH is held at PGND, allowing C BOOT to charge to
V DRV through the internal diode. When the PWM input goes
high, GH will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from C BOOT and
delivered to Q1's gate. As Q1 turns on, VSWH rises to V IN ,
forcing the BOOT pin to V IN +V C(BOOT) , which provides
sufficient V GS enhancement for Q1. To complete the switching
cycle, Q1 is turned off by pulling GH to VSWH. C BOOT is then
recharged to VDRV when VSWH falls to PGND. GH output is in
phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
SMOD
The SMOD (Skip Mode) function allows for higher converter
efficiency under light load conditions. During SMOD, the LS
FET is disabled and it prevents discharging of output caps.
When the SMOD# pin is pulled high, the sync buck converter
will work in synchronous mode. When the SMOD# pin is pulled
low, the LS FET is turned off. The SMOD function does not have
internal current sensing. This SMOD# pin is connected to a
PWM controller which enables or disables the SMOD
automatically when the controller detects light load condition.
Normally this pin is Active Low.
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 4 for the
relevant timing waveforms.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the GL pin. When the PWM signal goes HIGH, Q2 will begin
to turn OFF after some propagation delay (t PDLL ). Once the GL
pin is discharged below 1 V, Q1 begins to turn ON after adaptive
delay t DTHH .
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the
VSWH pin. When the PWM signal goes LOW, Q1 will begin to
turn OFF after some propagation delay (t PDHL ). Once the
VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive
delay t DTLH .
Additionally, V GS of Q1 is monitored. When V GS(Q1) is
discharged low, a secondary adaptive delay is initiated, which
results in Q2 being driven ON after 250 ns , regardless of VSWH
state. This function is implemented to ensure C BOOT is
recharged each switching cycle, particularly for cases where the
power convertor is sinking current and VSWH voltage does not
fall below the 1 V adaptive threshold. The 250 ns secondary
delay is longer than t DTLH .
FDMF6704A Rev. F
5
www.fairchildsemi.com
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