参数资料
| 型号： | FDMF6820B |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | MODULE DRMOS 55A 40-PQFN |
| 标准包装： | 1 |
| 系列： | XS™ DrMOS |
| 类型： | 高端/低端驱动器 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 电流 - 输出 / 通道： | 55A |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-PowerTFQFN |
| 供应商设备封装： | 40-PQFN（6x6） |
| 包装： | 标准包装 |
| 其它名称： | FDMF6820BFSDKR |
Functional Description
The FDMF6820B is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1 MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an Under-Voltage Lockout
(UVLO) circuit. When V CIN rises above ~3.1 V, the driver
is enabled. When V CIN falls below ~2.7 V, the driver is
disabled (GH, GL=0). The driver can also be disabled by
pulling the DISB# pin LOW (DISB# < V IL_DISB ), which
holds both GL and GH LOW regardless of the PWM
input state. The driver can be enabled by raising the
DISB# pin voltage HIGH (DISB# > V IH_DISB ).
Three-State PWM Input
The FDMF6820B incorporates a three-state 3.3 V PWM
input gate drive design. The three-state gate drive has
both logic HIGH level and LOW level, along with a
three-state shutdown window. When the PWM input
signal enters and remains within the three-state window
for a defined hold-off time (t D_HOLD-OFF ), both GL and GH
are pulled LOW. This enables the gate drive to shut
down both high-side and low-side MOSFETs to support
features such as phase shedding, which is common on
multi-phase voltage regulators.
Exiting Three-State Condition
When exiting a valid three-state condition, the
FDMF6820B follows the PWM input command. If the
Table 1.
UVLO
UVLO and Disable Logic
DISB# Driver State
PWM input goes from three-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
0
1
X
0
Disabled (GH, GL=0)
Disabled (GH, GL=0)
on. This is illustrated in Figure 27. The FDMF6820B
design allows for short propagation delays when exiting
the three-state window (see Electrical Characteristics) .
1 1 Enabled ( see Table 2 )
1 Open Disabled (GH, GL=0)
Note:
3. DISB# internal pull-down current source is 10 μA.
Thermal Warning Flag (THWN#)
The FDMF6820B provides a thermal warning flag
(THWN#) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, which can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced, low-R DS(ON) , N-channel MOSFET. The bias
for GL is internally connected between the VDRV and
CGND pins. When the driver is enabled, the driver's
output is 180° out of phase with the PWM input. When
the driver is disabled (DISB#=0 V), GL is held LOW.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (C BOOT ). During startup, V SWH is held
at PGND, allowing C BOOT to charge to V DRV through the
internal diode. When the PWM input goes HIGH, GH
begins to charge the gate of the high-side MOSFET (Q1).
Temperature
THWN#
Logic
State
HIGH
LOW
135°C Reset 150°C
Activation
Temperature
Normal Thermal
Operation Warning
During this transition, the charge is removed from C BOOT
and delivered to the gate of Q1. As Q1 turns on, V SWH
rises to V IN , forcing the BOOT pin to V IN + V BOOT , which
provides sufficient V GS enhancement for Q1. To complete
the switching cycle, Q1 is turned off by pulling GH to
V SWH . C BOOT is then recharged to V DRV when V SWH falls to
PGND. GH output is in-phase with the PWM input. The
high-side gate is held LOW when the driver is disabled or
the PWM signal is held within the three-state window for
longer than the three-state hold-off time, t D_HOLD-OFF .
T J_driver IC
Figure 26.
THWN Operation
? 2011 Fairchild Semiconductor Corporation
FDMF6820B ? Rev. 1.0.3
12
www.fairchildsemi.com
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相关代理商/技术参数 |
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| FDMF6820C | 功能描述:功率驱动器IC Xtra Small, Hi Perf, Hi Freq DrMOS Module RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| FDMF6821A | 功能描述:功率驱动器IC DrMOS 60A 3.3V RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| FDMF6821B | 功能描述:功率驱动器IC DrMOS 55A 3.3V RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| FDMF6821C | 功能描述:功率驱动器IC DrMOS 50A 3.3V RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| FDMF6823A | 功能描述:功率驱动器IC Xtra Small, Hi Perf, Hi Freq DrMOS Module RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
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