参数资料
型号: FDMF6820B
厂商: Fairchild Semiconductor
文件页数: 15/19页
文件大小: 0K
描述: MODULE DRMOS 55A 40-PQFN
标准包装: 1
系列: XS™ DrMOS
类型: 高端/低端驱动器
输入类型: PWM
输出数: 1
电流 - 输出 / 通道: 55A
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 40-PowerTFQFN
供应商设备封装: 40-PQFN(6x6)
包装: 标准包装
其它名称: FDMF6820BFSDKR
Application Information
Supply Capacitor Selection
For the supply inputs (V CIN ), a local ceramic bypass
capacitor is recommended to reduce noise and to
supply the peak current. Use at least a 1 μF X7R or X5R
capacitor. Keep this capacitor close to the VCIN pin and
connect it to the GND plane with vias.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C BOOT ), as shown in Figure 30. A bootstrap capacitance
of 100 nF X7R or X5R capacitor is usually adequate. A
series bootstrap resistor may be needed for specific
applications to improve switching noise immunity. The
VCIN Filter
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFET. In most cases,
it can be connected directly to VCIN, the pin that
provides power to the logic section of the driver. For
additional noise immunity, an RC filter can be inserted
between the VDRV and VCIN pins. Recommended
values would be 10 ? and 1 μF.
Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 30 for power loss testing method.
Power loss calculations are:
boot resistor may be required when operating above
15 V IN and is effective at controlling the high-side
MOSFET turn-on slew rate and V SHW overshoot. R BOOT
values from 0.5 to 3.0 ? are typically effective in
reducing VSWH overshoot.
P IN =(V IN x I IN ) + (V 5V x I 5V ) (W)
P SW =V SW x I OUT (W)
P OUT =V OUT x I OUT (W)
P LOSS_MODULE =P IN - P SW (W)
P LOSS_BOARD =P IN - P OUT (W)
EFF MODULE =100 x P SW /P IN (%)
EFF BOARD =100 x P OUT /P IN (%)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
? 2011 Fairchild Semiconductor Corporation
FDMF6820B ? Rev. 1.0.3
Figure 29.
Figure 30.
Block Diagram With V CIN Filter
Power Loss Measurement
15
www.fairchildsemi.com
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