参数资料
| 型号： | FDMF6833C |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | MODULE DRMOS 50A 40-PQFN |
| 标准包装： | 3,000 |
| 系列： | XS™ DrMOS |
| 类型： | 高端/低端驱动器 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 电流 - 输出 / 通道： | 50A |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-PowerTFQFN |
| 供应商设备封装： | 40-PQFN（6x6） |
| 包装： | 带卷 (TR) |
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead-time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 29
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
HIGH, Q2 begins to turn off after a propagation delay
(t PD_PHGLL ). Once the GL pin is discharged below 1.0 V,
Q1 begins to turn on after adaptive delay t D_DEADON .
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the GH-to-PHASE pin pair. When the PWM
signal goes LOW, Q1 begins to turn off after a
propagation delay (t PD_PLGHL ). Once the voltage across
GH-to-PHASE falls below 2.2 V, Q2 begins to turn on
after adaptive delay t D_DEADOFF .
V IH_PWM
t D_HOLD-OFF
V IH_PWM
V TRI_HI
V IH_PWM
V IH_PWM
V TRI_HI
V IL_PWM
V TRI_LO
PWM
t R_GH
t F_GH
V IL_PWM
90%
GH
to
10%
VSWH
V IN
VSWH
CCM
2.2V
t R_GL
DCM
t F_GL
DCM
V OUT
GL
90%
90%
1.0V
10%
10%
t PD_PHGLL
t PD_PLGHL
t PD_TSGHH
t D_HOLD-OFF
t PD_TSGHH
t D_HOLD-OFF t PD_TSGLH
t D_DEADON
t D_DEADOFF
Enter
3-state
Exit
3-state
Enter
3-state
Exit
3-state
Enter
3-state
Exit
3-state
Notes:
t PD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (t PD_PHGLL – PWM going HIGH to LS V GS (GL) going LOW)
t D_xxx = delay from IC generated signal to IC generated signal. Example (t D_DEADON – LS V GS (GL) LOW to HS V GS (GH) HIGH)
PWM
t PD_PHGLL = PWM rise to LS V GS fall, V IH_PWM to 90% LS V GS
t PD_PLGHL = PWM fall to HS V GS fall, V IL_PWM to 90% HS V GS
t PD_PHGHH = PWM rise to HS V GS rise, V IH_PWM to 10% HS V GS (SMOD# held LOW)
Exiting 3-state
t PD_TSGHH = PWM 3-state to HIGH to HS V GS rise, V IH_PWM to 10% HS V GS
t PD_TSGLH = PWM 3-state to LOW to LS V GS rise, V IL_PWM to 10% LS V GS
SMOD#
t PD_SLGLL = SMOD# fall to LS V GS fall, V IL_SMOD to 90% LS V GS
t PD_SHGLH = SMOD# rise to LS V GS rise, V IH_SMOD to 10% LS V GS
Figure 29.
? 2011 Fairchild Semiconductor Corporation
FDMF6833C ? Rev. 1.0.4
Dead Times
t D_DEADON = LS V GS fall to HS V GS rise, LS-comp trip value (~1.0V GL) to 10% HS V GS
t D_DEADOFF = VSWH fall to LS V GS rise, SW-comp trip value (~2.2V VSWH) to 10% LS V GS
PWM and 3-StateTiming Diagram
www.fairchildsemi.com
13
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