参数资料
型号: FDS8876
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: JFETs
英文描述: N-Channel PowerTrench MOSFET
中文描述: 12.5 A, 30 V, 0.0082 ohm, N-CHANNEL, Si, POWER, MOSFET
封装: SO-8
文件页数: 9/12页
文件大小: 262K
代理商: FDS8876
F
FDS8876 Rev. A
www.fairchildsemi.com
9
PSPICE Electrical Model
.SUBCKT FDS8876 2 1 3 ;
Ca 12 8 10.3e-10
Cb 15 14 10.3e-10
Cin 6 8 1.6e-9
rev January 2005
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.7
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.29e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 0.18e-10
RLgate 1 9 52.9
RLdrain 2 5 10
RLsource 3 7 1.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.6e-3
Rgate 9 20 2.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.8e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}
.MODEL DbodyMOD D (IS=2.0E-12 IKF=10 N=1.01 RS=5.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=5.7e-10 M=0.52 TT=7e-11 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=5.3e-10 IS=1e-30 N=10 M=0.37)
.MODEL MmedMOD NMOS (VTO=1.9 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3)
.MODEL MstroMOD NMOS (VTO=2.42 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.62 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=8.0e-3 TC2=1.0e-6)
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6)
.MODEL RvthresMOD RES (TC1=-2.0e-3 TC2=-6e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
-
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
19
VBAT
RVTHRES
IT
17
18
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
3
11
7
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
51
10
5
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
6
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